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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet_with_cop.v] - Blame information for rev 364

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1 189 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet_with_cop.v                                      ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 189 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001, 2002 Authors                             ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 302 markom
// Revision 1.4  2003/08/20 12:12:07  mohor
45
// Artisan RAMs added.
46
//
47 299 mohor
// Revision 1.3  2002/10/18 17:03:34  tadejm
48
// Changed BIST scan signals.
49
//
50 227 tadejm
// Revision 1.2  2002/10/11 13:29:28  mohor
51
// Bist signals added.
52
//
53 216 mohor
// Revision 1.1  2002/09/18 16:40:40  mohor
54
// Simple testbench that includes eth_cop, eth_host and eth_memory modules.
55
// This testbench is used for testing the whole environment. Use tb_ethernet
56
// testbench for testing just the ethernet MAC core (many tests).
57 189 mohor
//
58
//
59
//
60 216 mohor
//
61 189 mohor
 
62
 
63
 
64
`include "tb_eth_defines.v"
65 356 olof
`include "ethmac_defines.v"
66 189 mohor
`include "timescale.v"
67
 
68
module tb_ethernet_with_cop();
69
 
70
 
71
parameter Tp = 1;
72
 
73
 
74
reg           wb_clk_o;
75
reg           wb_rst_o;
76
 
77
reg           mtx_clk;
78
reg           mrx_clk;
79
 
80
wire   [3:0]  MTxD;
81
wire          MTxEn;
82
wire          MTxErr;
83
 
84
reg    [3:0]  MRxD;     // This goes to PHY
85
reg           MRxDV;    // This goes to PHY
86
reg           MRxErr;   // This goes to PHY
87
reg           MColl;    // This goes to PHY
88
reg           MCrs;     // This goes to PHY
89
 
90
wire          Mdi_I;
91
wire          Mdo_O;
92
wire          Mdo_OE;
93
wire          Mdc_O;
94
 
95
integer tx_log;
96
integer rx_log;
97
 
98
reg StartTB;
99
 
100
`ifdef ETH_XILINX_RAMB4
101
  reg gsr;
102
`endif
103
 
104
 
105
integer packet_ready_cnt, send_packet_cnt;
106
 
107
 
108
// Ethernet Slave Interface signals
109
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
110
wire  [3:0] eth_sl_wb_sel_i;
111
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
112
 
113
// Memory Slave Interface signals
114
wire [31:0] mem_sl_wb_adr_i, mem_sl_wb_dat_o, mem_sl_wb_dat_i;
115
wire  [3:0] mem_sl_wb_sel_i;
116
wire        mem_sl_wb_we_i, mem_sl_wb_cyc_i, mem_sl_wb_stb_i, mem_sl_wb_ack_o, mem_sl_wb_err_o;
117
 
118
// Ethernet Master Interface signals
119
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
120
wire  [3:0] eth_ma_wb_sel_o;
121
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
122
 
123 216 mohor
`ifdef ETH_WISHBONE_B3
124
wire  [2:0] eth_ma_wb_cti_o;
125
wire  [1:0] eth_ma_wb_bte_o;
126
`endif
127
 
128
 
129 189 mohor
// Host Master Interface signals
130
wire [31:0] host_ma_wb_adr_o, host_ma_wb_dat_i, host_ma_wb_dat_o;
131
wire  [3:0] host_ma_wb_sel_o;
132
wire        host_ma_wb_we_o, host_ma_wb_cyc_o, host_ma_wb_stb_o, host_ma_wb_ack_i, host_ma_wb_err_i;
133
 
134
 
135
 
136
eth_cop i_eth_cop
137
(
138
  // WISHBONE common
139
  .wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
140
 
141
  // WISHBONE MASTER 1  Ethernet Master Interface is connected here
142
  .m1_wb_adr_i(eth_ma_wb_adr_o),  .m1_wb_sel_i(eth_ma_wb_sel_o),  .m1_wb_we_i (eth_ma_wb_we_o),
143
  .m1_wb_dat_o(eth_ma_wb_dat_i),  .m1_wb_dat_i(eth_ma_wb_dat_o),  .m1_wb_cyc_i(eth_ma_wb_cyc_o),
144
  .m1_wb_stb_i(eth_ma_wb_stb_o),  .m1_wb_ack_o(eth_ma_wb_ack_i),  .m1_wb_err_o(eth_ma_wb_err_i),
145
 
146
  // WISHBONE MASTER 2  Host Interface is connected here
147
  .m2_wb_adr_i(host_ma_wb_adr_o), .m2_wb_sel_i(host_ma_wb_sel_o), .m2_wb_we_i (host_ma_wb_we_o),
148
  .m2_wb_dat_o(host_ma_wb_dat_i), .m2_wb_dat_i(host_ma_wb_dat_o), .m2_wb_cyc_i(host_ma_wb_cyc_o),
149
  .m2_wb_stb_i(host_ma_wb_stb_o), .m2_wb_ack_o(host_ma_wb_ack_i), .m2_wb_err_o(host_ma_wb_err_i),
150
 
151
  // WISHBONE slave 1   Ethernet Slave Interface is connected here
152
        .s1_wb_adr_o(eth_sl_wb_adr_i),  .s1_wb_sel_o(eth_sl_wb_sel_i),  .s1_wb_we_o (eth_sl_wb_we_i),
153
        .s1_wb_cyc_o(eth_sl_wb_cyc_i),  .s1_wb_stb_o(eth_sl_wb_stb_i),  .s1_wb_ack_i(eth_sl_wb_ack_o),
154
        .s1_wb_err_i(eth_sl_wb_err_o),  .s1_wb_dat_i(eth_sl_wb_dat_o),  .s1_wb_dat_o(eth_sl_wb_dat_i),
155
 
156
  // WISHBONE slave 2   Memory Interface is connected here
157
        .s2_wb_adr_o(mem_sl_wb_adr_i),  .s2_wb_sel_o(mem_sl_wb_sel_i),  .s2_wb_we_o (mem_sl_wb_we_i),
158
        .s2_wb_cyc_o(mem_sl_wb_cyc_i),  .s2_wb_stb_o(mem_sl_wb_stb_i),  .s2_wb_ack_i(mem_sl_wb_ack_o),
159
        .s2_wb_err_i(mem_sl_wb_err_o),  .s2_wb_dat_i(mem_sl_wb_dat_o),  .s2_wb_dat_o(mem_sl_wb_dat_i)
160
);
161
 
162
 
163
 
164
 
165
// Connecting Ethernet top module
166 364 olof
ethmac ethtop
167 189 mohor
(
168
  // WISHBONE common
169
  .wb_clk_i(wb_clk_o),              .wb_rst_i(wb_rst_o),
170
 
171
  // WISHBONE slave
172
        .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
173
        .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
174
        .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
175
 
176
  // WISHBONE master
177
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
178
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
179
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
180
 
181 216 mohor
`ifdef ETH_WISHBONE_B3
182
  .m_wb_cti_o(eth_ma_wb_cti_o),     .m_wb_bte_o(eth_ma_wb_bte_o),
183
`endif
184
 
185 189 mohor
  //TX
186
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
187
 
188
  //RX
189
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
190
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
191
 
192
  // MIIM
193
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
194
 
195
  .int_o()
196 216 mohor
 
197
  // Bist
198
`ifdef ETH_BIST
199 227 tadejm
  ,
200 302 markom
  .mbist_si_i       (1'b0),
201
  .mbist_so_o       (),
202
  .mbist_ctrl_i       (3'b001) // {enable, clock, reset}
203 216 mohor
`endif
204
 
205 189 mohor
);
206
 
207
 
208
 
209
// Connecting Memory Interface Module
210
eth_memory i_eth_memory
211
(
212
  // WISHBONE common
213
        .wb_clk_i(wb_clk_o),         .wb_rst_i(wb_rst_o),
214
 
215
  // WISHBONE slave:   Memory Interface is connected here
216
        .wb_adr_i(mem_sl_wb_adr_i),  .wb_sel_i(mem_sl_wb_sel_i),  .wb_we_i (mem_sl_wb_we_i),
217
        .wb_cyc_i(mem_sl_wb_cyc_i),  .wb_stb_i(mem_sl_wb_stb_i),  .wb_ack_o(mem_sl_wb_ack_o),
218
        .wb_err_o(mem_sl_wb_err_o),  .wb_dat_o(mem_sl_wb_dat_o),  .wb_dat_i(mem_sl_wb_dat_i)
219
);
220
 
221
 
222
// Connecting Host Interface
223
eth_host eth_host
224
(
225
  // WISHBONE common
226
  .wb_clk_i(wb_clk_o),         .wb_rst_i(wb_rst_o),
227
 
228
  // WISHBONE master
229
  .wb_adr_o(host_ma_wb_adr_o), .wb_sel_o(host_ma_wb_sel_o), .wb_we_o (host_ma_wb_we_o),
230
  .wb_dat_i(host_ma_wb_dat_i), .wb_dat_o(host_ma_wb_dat_o), .wb_cyc_o(host_ma_wb_cyc_o),
231
  .wb_stb_o(host_ma_wb_stb_o), .wb_ack_i(host_ma_wb_ack_i), .wb_err_i(host_ma_wb_err_i)
232
);
233
 
234
 
235
 
236
 
237
 
238
// Reset pulse
239
initial
240
begin
241
  MCrs=0;                                     // This should come from PHY
242
  MColl=0;                                    // This should come from PHY
243
  MRxD=0;                                     // This should come from PHY
244
  MRxDV=0;                                    // This should come from PHY
245
  MRxErr=0;                                   // This should come from PHY
246
  packet_ready_cnt = 0;
247
  send_packet_cnt = 0;
248
  tx_log = $fopen("ethernet_tx.log");
249
  rx_log = $fopen("ethernet_rx.log");
250
  wb_rst_o =  1'b1;
251
`ifdef ETH_XILINX_RAMB4
252
  gsr           =  1'b0;
253
  #100 gsr      =  1'b1;
254
  #100 gsr      =  1'b0;
255
`endif
256
  #100 wb_rst_o =  1'b0;
257
  #100 StartTB  =  1'b1;
258
end
259
 
260
`ifdef ETH_XILINX_RAMB4
261
  assign glbl.GSR = gsr;
262
`endif
263
 
264
 
265
 
266
// Generating wb_clk_o clock
267
initial
268
begin
269
  wb_clk_o=0;
270 216 mohor
//  forever #20 wb_clk_o = ~wb_clk_o;  // 2*20 ns -> 25 MHz    
271
  forever #12.5 wb_clk_o = ~wb_clk_o;  // 2*12.5 ns -> 40 MHz    
272 189 mohor
end
273
 
274
// Generating mtx_clk clock
275
initial
276
begin
277
  mtx_clk=0;
278
  #3 forever #20 mtx_clk = ~mtx_clk;   // 2*20 ns -> 25 MHz
279
end
280
 
281
// Generating mrx_clk clock
282
initial
283
begin
284
  mrx_clk=0;
285
  #16 forever #20 mrx_clk = ~mrx_clk;   // 2*20 ns -> 25 MHz
286
end
287
 
288
reg [31:0] tmp;
289
initial
290
begin
291
  wait(StartTB);  // Start of testbench
292
 
293
 
294
  eth_host.wb_write(`ETH_MODER, 4'hf, 32'h0); // Reset OFF
295
  eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
296
  eth_host.wb_write(`ETH_MAC_ADDR1, 4'hf, 32'h0002); // Set ETH_MAC_ADDR1 register
297
  eth_host.wb_write(`ETH_MAC_ADDR0, 4'hf, 32'h03040506); // Set ETH_MAC_ADDR0 register
298
 
299
  initialize_txbd(3);
300 216 mohor
  initialize_rxbd(4);
301 189 mohor
 
302
//  eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN  | `ETH_MODER_TXEN | `ETH_MODER_PRO | 
303
//                                      `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
304
//  eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN  | `ETH_MODER_TXEN | 
305
//                                      `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
306 216 mohor
//  eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN  | `ETH_MODER_TXEN | `ETH_MODER_BRO | 
307
//                                      `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
308 189 mohor
//  eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN  | `ETH_MODER_TXEN | `ETH_MODER_PRO | 
309
//                                      `ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK); // Set MODER register
310 216 mohor
  eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN  | `ETH_MODER_TXEN | `ETH_MODER_PRO |
311
                                      `ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK |
312
                                      `ETH_MODER_FULLD); // Set MODER register
313 189 mohor
  eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
314
 
315 216 mohor
  set_packet(16'h364, 8'h1);
316
  set_packet(16'h234, 8'h11);
317 189 mohor
  send_packet;
318 216 mohor
  repeat (1000) @(posedge mrx_clk);   // Waiting for TxEthMac to finish transmit
319
 
320
//  repeat (10000) @(posedge wb_clk_o);   // Waiting for TxEthMac to finish transmit
321
  set_packet(16'h534, 8'h21);
322
//  set_packet(16'h34, 8'h31);
323
 
324 189 mohor
/*
325
  eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h4);   // Enable Tx Flow control
326
  eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h5);   // Enable Tx Flow control
327
  eth_host.wb_write(`ETH_TX_CTRL, 4'hf, 32'h10013); // Send Control frame with PAUSE_TV=0x0013
328
*/
329 216 mohor
 
330 189 mohor
  send_packet;
331 216 mohor
  repeat (1000) @(posedge mrx_clk);   // Waiting for TxEthMac to finish transmit
332
  send_packet;
333
  repeat (1000) @(posedge mrx_clk);   // Waiting for TxEthMac to finish transmit
334 189 mohor
 
335 216 mohor
/*
336
  send_packet;
337
*/
338 189 mohor
 
339
 
340 216 mohor
  repeat (10000) @(posedge wb_clk_o);   // Waiting for TxEthMac to finish transmit
341 189 mohor
 
342 216 mohor
/*
343
  GetDataOnMRxD(113, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
344
 
345
  repeat (10000) @(posedge wb_clk_o);   // Waiting for TxEthMac to finish transmit
346
 
347 189 mohor
  GetDataOnMRxD(500, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
348
 
349
  repeat (1000) @(posedge mrx_clk);   // Waiting for TxEthMac to finish transmit
350
 
351
 
352
  GetDataOnMRxD(1200, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
353
 
354
 
355
  GetDataOnMRxD(1000, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
356
 
357
  repeat (10000) @(posedge wb_clk_o);   // Waiting for TxEthMac to finish transmit
358
 
359 216 mohor
*/
360 189 mohor
  // Reading and printing interrupts
361
  eth_host.wb_read(`ETH_INT, 4'hf, tmp);
362
  $display("Print irq = 0x%0x", tmp);
363
 
364
  //Clearing all interrupts
365
  eth_host.wb_write(`ETH_INT, 4'hf, 32'h60);
366
 
367
  // Reading and printing interrupts
368
  eth_host.wb_read(`ETH_INT, 4'hf, tmp);
369
  $display("Print irq = 0x%0x", tmp);
370
 
371
  $display("\n\n End of simulation");
372
  $stop;
373
 
374
 
375
 
376
end
377
 
378
 
379 216 mohor
`ifdef ETH_WISHBONE_B3
380 189 mohor
 
381 216 mohor
integer single_cnt_tx, burst_cnt_tx, burst_cnt;
382
integer single_cnt_rx, burst_cnt_rx;
383
 
384
initial
385
begin
386
single_cnt_tx=0; burst_cnt_tx=0; burst_cnt=0;
387
single_cnt_rx=0; burst_cnt_rx=0;
388
end
389
 
390
// Single and burst cycle watcher
391
always @ (posedge wb_clk_o)
392
begin
393
  if(eth_ma_wb_ack_i) begin
394
    if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
395
      if(burst_cnt!==0)
396
        $display("(%0t)(%m) ERROR !!!  burst_cnt should be 0 because this is a single access", $time);
397
      else
398
        single_cnt_rx=single_cnt_rx+1;
399
    end
400
    else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
401
      if(burst_cnt!==0)
402
        $display("(%0t)(%m) ERROR !!!  burst_cnt should be 0 because this is a single access", $time);
403
      else
404
        single_cnt_tx=single_cnt_tx+1;
405
    end
406
    else if(eth_ma_wb_cyc_o & eth_ma_wb_cti_o==3'b010) begin // burst in progress
407
      burst_cnt=burst_cnt+1;
408
    end
409
    else if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
410
      burst_cnt_rx=burst_cnt_rx+1;
411
      burst_cnt=0;
412
    end
413
    else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
414
      burst_cnt_tx=burst_cnt_tx+1;
415
      burst_cnt=0;
416
    end
417
    else
418
      $display("(%0t)(%m) ERROR !!!  Unknown cycle type or sequence", $time);
419
  end
420
end
421
`endif  // ETH_WISHBONE_B3
422
 
423
 
424
 
425 189 mohor
task initialize_txbd;
426
  input [6:0] txbd_num;
427
 
428
  integer i;
429
  integer bd_status_addr, buf_addr, bd_ptr_addr;
430
 
431
  for(i=0; i<txbd_num; i=i+1) begin
432
    buf_addr = `TX_BUF_BASE + i * 32'h600;
433
    bd_status_addr = `TX_BD_BASE + i * 8;
434
    bd_ptr_addr = bd_status_addr + 4;
435
 
436
    // Initializing BD - status
437
    if(i==txbd_num-1)
438
      eth_host.wb_write(bd_status_addr, 4'hf, 32'h00007800);    // last BD: + WRAP
439
    else
440
      eth_host.wb_write(bd_status_addr, 4'hf, 32'h00005800);    // IRQ + PAD + CRC
441
 
442
    eth_host.wb_write(bd_ptr_addr, 4'hf, buf_addr);             // Initializing BD - pointer
443
  end
444
endtask // initialize_txbd
445
 
446
 
447
task initialize_rxbd;
448
  input [6:0] rxbd_num;
449
 
450
  integer i;
451
  integer bd_status_addr, buf_addr, bd_ptr_addr;
452
 
453
  for(i=0; i<rxbd_num; i=i+1) begin
454
    buf_addr = `RX_BUF_BASE + i * 32'h600;
455
    bd_status_addr = `RX_BD_BASE + i * 8;
456
    bd_ptr_addr = bd_status_addr + 4;
457
 
458
    // Initializing BD - status
459
    if(i==rxbd_num-1)
460
      eth_host.wb_write(bd_status_addr, 4'hf, 32'h0000e000);    // last BD: + WRAP
461
    else
462
      eth_host.wb_write(bd_status_addr, 4'hf, 32'h0000c000);    // IRQ + PAD + CRC
463
 
464
    eth_host.wb_write(bd_ptr_addr, 4'hf, buf_addr);             // Initializing BD - pointer
465
  end
466
endtask // initialize_rxbd
467
 
468
 
469
task set_packet;
470
  input  [15:0] len;
471
  input   [7:0] start_data;
472
 
473
  integer i, sd;
474
  integer bd_status_addr, bd_ptr_addr, buffer, bd;
475
 
476
  begin
477
    sd = start_data;
478
    bd_status_addr = `TX_BD_BASE + packet_ready_cnt * 8;
479
    bd_ptr_addr = bd_status_addr + 4;
480
 
481
    // Reading BD + buffer pointer
482
    eth_host.wb_read(bd_status_addr, 4'hf, bd);
483
    eth_host.wb_read(bd_ptr_addr, 4'hf, buffer);
484
 
485
    while(bd & `ETH_TX_BD_READY) begin  // Buffer is ready. Don't touch !!!
486
      repeat(100) @(posedge wb_clk_o);
487
      i=i+1;
488
      eth_host.wb_read(bd_status_addr, 4'hf, bd);
489
      if(i>1000)  begin
490
        $display("(%0t)(%m)Waiting for TxBD ready to clear timeout", $time);
491
        $stop;
492
      end
493
    end
494
 
495
    // First write might not be word allign.
496
    if(buffer[1:0]==1)  begin
497
      eth_host.wb_write(buffer-1, 4'h7, {8'h0, sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2});
498
      sd=sd+3;
499
      i=3;
500
    end
501
    else if(buffer[1:0]==2)  begin
502
      eth_host.wb_write(buffer-2, 4'h3, {16'h0, sd[7:0], sd[7:0]+3'h1});
503
      sd=sd+2;
504
      i=2;
505
    end
506
    else if(buffer[1:0]==3)  begin
507
      eth_host.wb_write(buffer-3, 4'h1, {24'h0, sd[7:0]});
508
      sd=sd+1;
509
      i=1;
510
    end
511
    else
512
      i=0;
513
 
514
 
515
    for(i=i; i<len-4; i=i+4) begin   // Last 0-3 bytes are not written
516
      eth_host.wb_write(buffer+i, 4'hf, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, sd[7:0]+3'h3});
517
      sd=sd+4;
518
    end
519
 
520
 
521
    // Last word
522
    if(len-i==3)
523
      eth_host.wb_write(buffer+i, 4'he, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, 8'h0});
524
    else if(len-i==2)
525
      eth_host.wb_write(buffer+i, 4'hc, {sd[7:0], sd[7:0]+3'h1, 16'h0});
526
    else if(len-i==1)
527
      eth_host.wb_write(buffer+i, 4'h8, {sd[7:0], 24'h0});
528
    else if(len-i==4)
529
      eth_host.wb_write(buffer+i, 4'hf, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, sd[7:0]+3'h3});
530
    else
531
      $display("(%0t)(%m) ERROR", $time);
532
 
533
 
534
    // Checking WRAP bit
535
    if(bd & `ETH_TX_BD_WRAP)
536
      packet_ready_cnt = 0;
537
    else
538
      packet_ready_cnt = packet_ready_cnt+1;
539
 
540
    // Writing len to bd
541
    bd = bd | (len<<16);
542
    eth_host.wb_write(bd_status_addr, 4'hf, bd);
543
 
544
  end
545
endtask // set_packet
546
 
547
 
548
task send_packet;
549
 
550
  integer bd_status_addr, bd_ptr_addr, buffer, bd;
551
 
552
  begin
553
    bd_status_addr = `TX_BD_BASE + send_packet_cnt * 8;
554
    bd_ptr_addr = bd_status_addr + 4;
555
 
556
    // Reading BD + buffer pointer
557
    eth_host.wb_read(bd_status_addr, 4'hf, bd);
558
    eth_host.wb_read(bd_ptr_addr, 4'hf, buffer);
559
 
560
    if(bd & `ETH_TX_BD_WRAP)
561
      send_packet_cnt=0;
562
    else
563
      send_packet_cnt=send_packet_cnt+1;
564
 
565
    // Setting ETH_TX_BD_READY bit
566
    bd = bd | `ETH_TX_BD_READY;
567
    eth_host.wb_write(bd_status_addr, 4'hf, bd);
568
  end
569
 
570
 
571
endtask // send_packet
572
 
573
 
574
task GetDataOnMRxD;
575
  input [15:0] Len;
576
  input [31:0] TransferType;
577
  integer tt;
578
 
579
  begin
580
    @ (posedge mrx_clk);
581
    #1MRxDV=1'b1;
582
 
583
    for(tt=0; tt<15; tt=tt+1)
584
      begin
585
        MRxD=4'h5;              // preamble
586
        @ (posedge mrx_clk);
587
        #1;
588
      end
589
 
590
    MRxD=4'hd;                // SFD
591
 
592
    for(tt=1; tt<(Len+1); tt=tt+1)
593
      begin
594
        @ (posedge mrx_clk);
595
        #1;
596
            if(TransferType == `UNICAST_XFR && tt == 1)
597
                MRxD= 4'h0;   // Unicast transfer
598
              else if(TransferType == `BROADCAST_XFR && tt < 7)
599
                MRxD = 4'hf;
600
              else
601
          MRxD=tt[3:0]; // Multicast transfer
602
 
603
        @ (posedge mrx_clk);
604
              #1;
605
              if(TransferType == `BROADCAST_XFR && tt < 7)
606
                MRxD = 4'hf;
607
              else
608
          MRxD=tt[7:4];
609
      end
610
 
611
    @ (posedge mrx_clk);
612
    #1;
613
    MRxDV=1'b0;
614
  end
615
endtask // GetDataOnMRxD
616
 
617
 
618
endmodule

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