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1 363 unneback
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2011 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors.  Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
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# Date created = 14:13:08  August 09, 2011
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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#               ethmac_assignment_defaults.qdf
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#    If this file doesn't exist, see file:
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#               assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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#    file is updated automatically by the Quartus II software
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#    and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE22F17C9L
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set_global_assignment -name TOP_LEVEL_ENTITY ethmac
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:13:08  AUGUST 09, 2011"
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set_global_assignment -name LAST_QUARTUS_VERSION "11.0 SP1"
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set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac.v
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 9L
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.0V

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