Subversion Repositories ethmac

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2011 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II

# Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition

# Date created = 14:13:08  August 09, 2011

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               ethmac_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name DEVICE EP4CE22F17C9L

set_global_assignment -name TOP_LEVEL_ENTITY ethmac

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:13:08  AUGUST 09, 2011"

set_global_assignment -name LAST_QUARTUS_VERSION "11.0 SP1"

set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac.v

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 9L

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.0V