部分翻译
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
363 |
unneback |
VERILOG_FILES = eth_clockgen.v
|
| 2 |
|
|
VERILOG_FILES += eth_cop.v
|
| 3 |
|
|
VERILOG_FILES += eth_crc.v
|
| 4 |
|
|
VERILOG_FILES += eth_defines.v
|
| 5 |
|
|
VERILOG_FILES += eth_fifo.v
|
| 6 |
|
|
VERILOG_FILES += eth_maccontrol.v
|
| 7 |
|
|
VERILOG_FILES += eth_macstatus.v
|
| 8 |
|
|
VERILOG_FILES += eth_miim.v
|
| 9 |
|
|
VERILOG_FILES += eth_outputcontrol.v
|
| 10 |
|
|
VERILOG_FILES += eth_random.v
|
| 11 |
|
|
VERILOG_FILES += eth_receivecontrol.v
|
| 12 |
|
|
VERILOG_FILES += eth_registers.v
|
| 13 |
|
|
VERILOG_FILES += eth_register.v
|
| 14 |
|
|
VERILOG_FILES += eth_rxaddrcheck.v
|
| 15 |
|
|
VERILOG_FILES += eth_rxcounters.v
|
| 16 |
|
|
VERILOG_FILES += eth_rxethmac.v
|
| 17 |
|
|
VERILOG_FILES += eth_rxstatem.v
|
| 18 |
|
|
VERILOG_FILES += eth_shiftreg.v
|
| 19 |
|
|
VERILOG_FILES += eth_spram_256x32.v
|
| 20 |
|
|
VERILOG_FILES += eth_transmitcontrol.v
|
| 21 |
|
|
VERILOG_FILES += eth_txcounters.v
|
| 22 |
|
|
VERILOG_FILES += eth_txethmac.v
|
| 23 |
|
|
VERILOG_FILES += eth_txstatem.v
|
| 24 |
|
|
VERILOG_FILES += eth_wishbone.v
|
| 25 |
|
|
VERILOG_FILES += eth_top.v
|
| 26 |
|
|
VERILOG_FILES += xilinx_dist_ram_16x32.v
|
| 27 |
|
|
|
| 28 |
|
|
|
| 29 |
362 |
unneback |
config:
|
| 30 |
|
|
configurator eth_defines.v
|
| 31 |
363 |
unneback |
|
| 32 |
|
|
.PHONY: ethmac.v
|
| 33 |
|
|
ethmac.v: $(VERILOG_FILES)
|
| 34 |
|
|
vppreproc --simple $(VERILOG_FILES) > ethmac.v
|
© copyright 1999-2013
OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.