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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [prgen_fifo.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:00 2011
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//--
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//-- Source file: prgen_fifo.v
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//---------------------------------------------------------
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module prgen_fifo(clk,reset,push,pop,din,dout,empty,full);
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   parameter                  WIDTH      = 8;
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   parameter                  DEPTH_FULL = 8;
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   parameter               SINGLE     = DEPTH_FULL == 1;
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   parameter               DEPTH      = SINGLE ? 1 : DEPTH_FULL -1;
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   parameter               DEPTH_BITS =
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                  (DEPTH <= 2)   ? 1 :
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                  (DEPTH <= 4)   ? 2 :
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                  (DEPTH <= 8)   ? 3 :
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                  (DEPTH <= 16)  ? 4 :
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                  (DEPTH <= 32)  ? 5 :
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                  (DEPTH <= 64)  ? 6 :
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                  (DEPTH <= 128) ? 7 :
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                  (DEPTH <= 256) ? 8 : 0; //0 is ilegal
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   parameter               LAST_LINE  = DEPTH-1;
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   input                      clk;
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   input                      reset;
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   input               push;
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   input               pop;
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   input [WIDTH-1:0]           din;
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   output [WIDTH-1:0]           dout;
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   //output               next;
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   output               empty;
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   output               full;
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   wire               reg_push;
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   wire               reg_pop;
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   wire               fifo_push;
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   wire               fifo_pop;
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   reg [DEPTH-1:0]           fullness_in;
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   reg [DEPTH-1:0]           fullness_out;
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   reg [DEPTH-1:0]           fullness;
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   reg [WIDTH-1:0]           fifo [DEPTH-1:0];
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   wire               fifo_empty;
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   wire               next;
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   reg [WIDTH-1:0]           dout;
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   reg                   dout_empty;
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   reg [DEPTH_BITS-1:0]       ptr_in;
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   reg [DEPTH_BITS-1:0]       ptr_out;
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   assign               reg_push  = push & fifo_empty & (dout_empty | pop);
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   assign               reg_pop   = pop & fifo_empty;
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   assign               fifo_push = !SINGLE & push & (~reg_push);
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   assign               fifo_pop  = !SINGLE & pop & (~reg_pop);
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   always @(posedge clk or posedge reset)
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     if (reset)
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       begin
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      dout       <= #1 {WIDTH{1'b0}};
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      dout_empty <= #1 1'b1;
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       end
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     else if (reg_push)
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       begin
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      dout       <= #1 din;
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      dout_empty <= #1 1'b0;
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       end
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     else if (reg_pop)
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       begin
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      dout       <= #1 {WIDTH{1'b0}};
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      dout_empty <= #1 1'b1;
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       end
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     else if (fifo_pop)
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       begin
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      dout       <= #1 fifo[ptr_out];
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      dout_empty <= #1 1'b0;
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       end
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   always @(posedge clk or posedge reset)
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     if (reset)
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       ptr_in <= #1 {DEPTH_BITS{1'b0}};
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     else if (fifo_push)
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       ptr_in <= #1 ptr_in == LAST_LINE ? 0 : ptr_in + 1'b1;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       ptr_out <= #1 {DEPTH_BITS{1'b0}};
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     else if (fifo_pop)
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       ptr_out <= #1 ptr_out == LAST_LINE ? 0 : ptr_out + 1'b1;
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   always @(posedge clk)
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     if (fifo_push)
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       fifo[ptr_in] <= #1 din;
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   always @(/*AUTOSENSE*/fifo_push or ptr_in)
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     begin
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    fullness_in = {DEPTH{1'b0}};
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    fullness_in[ptr_in] = fifo_push;
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     end
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   always @(/*AUTOSENSE*/fifo_pop or ptr_out)
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     begin
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    fullness_out = {DEPTH{1'b0}};
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    fullness_out[ptr_out] = fifo_pop;
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     end
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   always @(posedge clk or posedge reset)
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     if (reset)
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       fullness <= #1 {DEPTH{1'b0}};
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     else if (fifo_push | fifo_pop)
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       fullness <= #1 (fullness & (~fullness_out)) | fullness_in;
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   assign next       = |fullness;
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   assign fifo_empty = ~next;
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   assign empty      = fifo_empty & dout_empty;
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   assign full       = SINGLE ? !dout_empty : &fullness;
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endmodule
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