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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb32/] [dma_ahb32_core0_arbiter.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:31:22 2011
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//--
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//-- Source file: dma_core_arbiter.v
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//---------------------------------------------------------
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module dma_ahb32_core0_arbiter(clk,reset,enable,joint_mode,page_cross,joint_req,prio_top,prio_high,prio_top_num,prio_high_num,hold,ch_ready,ch_active,finish,ch_go_out,ch_num,ch_last);
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   parameter                CH_LAST       = 1-1;
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   input             clk;
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   input             reset;
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   input             enable;
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   input             joint_mode;
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   input             page_cross;
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   input             joint_req;
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   input             prio_top;
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   input             prio_high;
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   input [2:0]             prio_top_num;
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   input [2:0]             prio_high_num;
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   input             hold;
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   input [7:0]             ch_ready;
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   input [7:0]             ch_active;
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   input             finish;
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   output             ch_go_out;
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   output [2:0]         ch_num;
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   output             ch_last;
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   reg [7:0]             current_active;
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   wire             current_ready_only;
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   wire             ch_last_pre;
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   wire             ch_last;
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   wire             ready;
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   wire             next_ready;
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   wire             next_ready0;
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   wire             next_ready1;
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   wire             prio_top_ready;
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   wire             prio_high_ready;
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   reg                 in_prog;
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   wire             ch_go_pre;
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   wire             ch_go_pre_d;
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   wire             ch_go_top_pre;
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   wire             ch_go_high_pre;
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   wire             ch_go;
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   wire             ch_go_d;
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   wire             ch_go_top;
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   wire             ch_go_high;
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   wire             ch_go_next;
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   wire             hold_d;
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   wire             advance_next;
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   wire [2:0]             ch_num_pre;
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   wire [3:0]             next_ch_num0_pre;
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   wire [3:0]             next_ch_num0_pre2;
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   wire [2:0]             next_ch_num0;
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   wire [3:0]             next_ch_num1_pre;
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   wire [3:0]             next_ch_num1_pre2;
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   wire [2:0]             next_ch_num1;
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   wire [2:0]             next_ch_num_pre;
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   assign             ch_go_out = 'd1;
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   assign             ch_num    = 'd0;
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   assign             ch_last   = 'd1;
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endmodule
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