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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC/] [scc_scripts/] [run_imp_sort.tcl] - Blame information for rev 17

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Line No. Rev Author Line
1 17 sumanta.chaudhuri
set_project_params -directory ./
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set_project_params -results myboard.txt
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set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
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set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
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set_project_params -cache_result_files no
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set_project_params -cache_data_files yes
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if [file exists imp_sort] { delete_implementation imp_sort }
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create_implementation imp_sort
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set_implementation_params -systemc_source no
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set_implementation_params -instream_boundary_register infer
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set_implementation_params -memory_return_path_external_delay 0%
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set_implementation_params -memory_forward_path_external_delay 0%
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set_implementation_params -instream_forward_path_external_delay 0%
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set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g"
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set_implementation_params -outstream_return_path_external_delay 0%
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set_implementation_params -appfile synth_src/threats.cpp
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set_implementation_params -proc streamsort
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set_implementation_params -memory_forward_boundary_register infer
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set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
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#set_implementation_params -techlib altera-cyclone4gx
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#set_implementation_params -device ep4cgx110c-fc23-7
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set_implementation_params -techlib xilinx-spartan6
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set_implementation_params -device xc6slx45-csg324-2
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set_implementation_params -memory_return_boundary_register infer
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set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
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set_implementation_params -host_memory_access never
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set_implementation_params -init_data_registers yes
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set_implementation_params -outstream_forward_path_external_delay 0%
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set_implementation_params -outstream_boundary_register infer
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set_implementation_params -build_tcab yes
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set_implementation_params -reset_data_registers yes
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set_implementation_params -task_overlap infer
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set_implementation_params -instream_return_path_external_delay 0%
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set_implementation_params -simulator modelsim
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set_implementation_params -clock_freq 100
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set_loop_params -ii 1
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csim  -golden  -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
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preprocess
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csim  -preprocess  -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
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schedule
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csim  -schedule  -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
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synthesize
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create_rtl_package  -force
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