Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other Stage: Any stage planning mature alpha beta stable License: Any license GPL LGPL BSD Others
ASIC proven Design done FPGA proven Specification done OpenCores Certified

marked with

Arithmetic core 13

Prototype board 5

Communication controller 22

Crypto core 9

DSP core 3

ECC core 3

Library 1

Memory core 4

Other 13

Processor 22

System on Chip 8

System controller 3

Video controller 10