Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other Stage: Any stage planning mature alpha beta stable License: Any license GPL LGPL BSD Others
ASIC proven Design done FPGA proven Specification done OpenCores Certified

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Arithmetic core 24

Prototype board 4

Communication controller 63

Crypto core 19

DSP core 10

ECC core 4

Library 3

Memory core 13

Other 39

Processor 57

System on Chip 16

System controller 5

Testing / Verification 4

Video controller 22