Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other Stage: Any stage planning mature alpha beta stable License: Any license GPL LGPL BSD Others
ASIC proven Design done FPGA proven Specification done OpenCores Certified

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Arithmetic core 33

Prototype board 8

Communication controller 47

Crypto core 17

DSP core 9

ECC core 8

Library 4

Memory core 16

Other 32

Processor 46

System on Chip 11

System controller 8

Testing / Verification 2

Video controller 13