Single Slot PCM Interface :: Overview
Project maintainers
Details
Name: ss_pcm
Created: Sep 17, 2002
Updated: Feb 10, 2004
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
FPGA proven
WishBone Compliant: No
License:
Description
Simple PCM Interface. Allows to interface to such popular devices
like TI DSPs (via McBSP bus) in PCM mode. Of course many more
applications. Very small and simple core.
Features
- Implemented in Verilog
- Frame Start position adjustable
- full 16 bit frames
- 1 Receive holding register
- 1 Transmit holding Register
- Fully Synthesisable
- Can handle PCM streams at any rate, 128KHz to 100MHz.
- 38 LUTs in a Spartan II