OpenCores

SPI Master/Slave Interface :: News

News

Jan 5, 2013 Working on hardening the FSM control register with a Hamming code self-correcting logic.
Nov 30, 2012 Changes in the project page
Sep 21, 2011 Updated information on ISE 12.1
Aug 30, 2011 Updated SVN files with clarified licensing, added full LGPL license text to the SVN trunk.
Aug 29, 2011 Added license discussion term
Aug 29, 2011 Updated SVN with fix for MISO preload mux.
Aug 19, 2011 Update HTML for description
Aug 19, 2011 Updated FPGA test data
Aug 19, 2011 Updated development status
Aug 14, 2011 Verification info
Aug 14, 2011 Verification data
Aug 14, 2011 Updated Project
Aug 13, 2011 Updated project.
Aug 11, 2011 Clarified description of operation.
Aug 11, 2011 Updated SVN, added complete verification ISE project, changed description.
Aug 10, 2011 Updated links in description
Aug 9, 2011 updated SVN for spi_slave.vhd
Aug 9, 2011 Updated SVN files and description, to fix slave continuous transfer mode bug.
Aug 7, 2011 Changed project description.
Aug 5, 2011 Fixed "assert PREFETCH >= 1" at spi master. SVN files updated.
Aug 3, 2011 Updated description at development status section.
Aug 3, 2011 Updated documentation (specification manual and verification data).
Aug 2, 2011 Cores are DELIVERED. Passed verification tests at 50MHz, for all SPI modes. Ready to be used.
Aug 2, 2011 Updated scope photos. Updated SVN files. Cores working for continuous transfer at all spi modes.
Aug 1, 2011 Simulated continuous transfer mode. Will update the SVN after verification in FPGA.
Aug 1, 2011 Updated verification info and scope pictures.
Jul 31, 2011 Updated verification info.
Jul 30, 2011 Updated project description.
Jul 29, 2011 spi_slave.vhd [v2.00.0110]: The slave core is redesigned and works for all SPI modes. Check scope photos.
Jul 29, 2011 Added hardware scope screenshot
Jul 29, 2011 Update project data and SVN files.
Jul 25, 2011 v1.13.0125: The master core is fixed for CPHA='1'. Working on the slave core for the CPHA='1' cases. Will upload SVN files today.
Jul 17, 2011 Updated documentation.
Jul 17, 2011 Updated SVN files.
Jul 17, 2011 Updated SVN files. Verified both cores in loopback for 50MHz SPI clock.
Jul 16, 2011 Core verified. Changed status to Stable.
Jul 13, 2011 Updated verification info.
Jul 13, 2011 Updated SVN files. Minor changes and documentation updates.
Jul 12, 2011 Update documentation and SVN files
Jul 11, 2011 Updated SVN files, correcting some old comment leftovers.
Jul 11, 2011 Updated SVN files, with new version of the spi_master.vhd and scope screenshots.
Jul 9, 2011 Updated information on silicon verification and slock streamlining.
Jul 8, 2011 Verified in silicon in the Atlys board, at 12.5MHz and 25MHz.
Jun 20, 2011 Uptated synthesis info.
Jun 16, 2011 v0.97.0086: Uploaded new SVN version, fixed bugs, improved design.
Jun 15, 2011 Atetntion: due to a proxy barrier, I'm temporarily unable to upload SVN updates. Working on it.
Jun 15, 2011 New version fixes CPHA bugs and data transfer between clocks.
Jun 13, 2011 Updated results of synthesis.
Jun 7, 2011 Updated project description. Comitted SVN new revision.
May 30, 2011 v0.95.0050: uploaded project files.
May 22, 2011 Updated description and design frequency.
May 18, 2011 Updated description
May 18, 2011 Added features block
May 18, 2011 Updated project description.
May 18, 2011 Updated project description.
May 18, 2011 Change project category to "communications controller". Upload source files.
© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.