Coprocessor-ready SPARC V8 core :: Overview

Project maintainers


Name: sparcv8coprocessor
Created: Jun 14, 2012
Updated: Aug 30, 2012
SVN: No files checked in

Other project properties

Category: Processor
Language: Verilog
Development status: Planning
Additional info: none
WishBone Compliant: No
License: LGPL


The SPARC V8 instruction set has a well-defined opcode space and model for coprocessor instructions; this includes 25 bits of instruction space for data-processing instructions, as well as predefined instructions for loads/stores to/from coprocessor registers, and branch-on-coprocessor condition codes. The goal of this project is to make a synthesizable SPARC V8 compatible core with a well-documented internal interface to a coprocessor. The intention is to facilitate a close coupling of custom logic to the CPU core, while minimizing the redesign necessary in the CPU.

First FPGA implementation will likely be on a Xilinx Zynq 7020, unless something with a more compelling $/gate ratio than the Zedboard comes out soon. As such, initial implementations of the processor are likely to use the AXI bus as the system interface, as this is the interface to most of the hardwired components in the Zynq (memory controller, on-chip-SRAM, etc). Once the core itself is ironed out, a Wishbone compatible variant will be made.

The high-level specifications are due to be completed mid-September. Work on the HDL will commence shortly thereafter, but expect progress to be slow.

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