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*openMSP430 :: News
News

News

Apr 22, 2012 Add Google+ link
Mar 22, 2012 ASIC proven :-)
Mar 22, 2012 Adjust image size for the HTML documentation
Mar 22, 2012 Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.
Oct 24, 2011 ASIC teaser :-)
Oct 19, 2011 Fixed failing image links in the online documentation.
Aug 9, 2011 test
Jul 25, 2011 Thanks to Ricardo Ribalda Delgado an new FPGA example is available: Avnet Spartan-6 LX9 microboard
Jun 23, 2011 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.
Jun 7, 2011 Update online documentation to reflect the latest design status.
May 20, 2011 Note that the per_addr bus width goes from 8 to 14 bits and that your custom peripherals address decoders must be updated accordingly.
May 20, 2011 Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
Mar 1, 2011 Update online documentation with Actel's FPGA implementation example
Feb 24, 2011 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: Icarus Verilog, Cver, Verilog-XL, NCVerilog, Modelsim
Feb 20, 2011 Bug Fix (SVN revision 92): When the CPU is Halted through the serial debug interface and if an IRQ occures during this time, then the CPU will go wild when the CPU goes out of halt mode.
Feb 12, 2011 Software development tools update: new Minidebug interface, Intel-HEX files are now supported
Dec 16, 2010 Add Actel ProASIC3 example project with SpaceWar oscilloscope game demo :-)
Aug 28, 2010 Update serial debug interface to support memories whose sizes are not a power of 2.
Aug 1, 2010 Expand configurability of the program and data memory sizes.
May 15, 2010 add link to discussion group
Apr 25, 2010 The openMSP430 is now listed by TI on its open source projects list: http://processors.wiki.ti.com/index.php/Open_Source_Projects_-_MSP430
Mar 7, 2010 Add online documentation section: Area and Speed analysis
Mar 7, 2010 16x16 Hardware Multiplier is available :-)
Feb 2, 2010 Exclude the range mode from the Hardware breakpoint units by default as it is not used by GDB.
Jan 22, 2010 Add online documentation section: Integration and connectivity
Jan 4, 2010 change image properties in html documentation for proper rendering in google Chrome browser
Dec 29, 2009 Update the online documentation to reflect the latest Verilog changes.
Dec 29, 2009 In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_*" ports and defines to "pmem_*" (program memory). - renamed the "ram_*" ports and defines to "dmem_*" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.
Dec 29, 2009 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.
Dec 27, 2009 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution) + diverse minor updates in the documentation.
Dec 27, 2009 HTML documentation (Overview): Update limitation section
Sep 20, 2009 Windows Users: Some batch files have been created so that you can now run the FPGA Xilinx flow from windows (assuming that ISE is installed on your system).
Aug 30, 2009 The defines are now directly included (with the `include construct) in the Verilog files.
Aug 30, 2009 replaced "openMSP430.inc" with "openMSP430_defines.v"
Aug 25, 2009 Added the "Specification done" tag
Aug 17, 2009 Updated some links in the "Core" documentation
Aug 17, 2009 Updated some links
Aug 5, 2009 Updated all source code headers with SVN keywords
Aug 4, 2009 Completed documentation
Jul 12, 2009 Serial debug interface documentation completed
Jul 1, 2009 Project has been uploaded to the SVN repository. Documentation on going.
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