OpenCores

*openMSP430 :: Core
Core

Table of content

1. Introduction

The openMSP430 is a 16-bit microcontroller core compatible with TI's MSP430 family (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.

Depending on the selected configuration, this design can either be:
      •  FPGA friendly: the core doesn't contain any clock gate and has only a single clock domain. As a consequence, in this mode, the Basic Clock Module peripheral has a few limitations.

      •  ASIC friendly: the core contains up to all clock management options (clock muxes & low-power modes, fine grained clock gating, ...) and is also ready for scan insertion. In this mode, the Basic Clock Module offers all features listed in the official documentation.

It is to be noted that this IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration). However the core is fully configurable in regard to the supported RAM and/or ROM sizes.

In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.

2. Design

2.1 Core

2.1.1 Design structure

The following diagram shows the openMSP430 design structure:

CPU Structure
  • Frontend: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.
  • Execution unit: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.
  • Serial Debug Interface: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard two-wire 8N1 serial interface.
  • Memory backbone: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.
  • Basic Clock Module: Generates MCLK, ACLK, SMCLK and manage the low power modes.
  • SFRs: The Special Function Registers block contain diverse configuration registers (NMI, Watchdog, ...).
  • Watchdog: Although it is a peripheral, the watchdog is directly included in the core because of its tight links with the NMI interrupts and PUC reset generation.
  • 16x16 Multiplier: The hardware multiplier peripheral is transparently supported by the GCC compiler and is therefore located in the core. It can be included or excluded at will through a Verilog define.

2.1.2 Limitations

The known core limitations are the following:
  • Instructions can't be executed from the data memory.

2.1.3 Configuration

It is possible to configure the openMSP430 core through the openMSP430_defines.v file located in the rtl directory (see file and directory description).
In this section, three sets of adjustabe user parameters are discussed in order to customize the core. A fourth set is available for ASIC specific options and will be discussed in the ASIC implementation section.

2.1.3.1 Basic System Configuration

The basic system can be adjusted with the following set of defines in order to match the target system requirements.




//============================================================================
//============================================================================
// BASIC SYSTEM CONFIGURATION
//============================================================================
//============================================================================
//
// Note: the sum of program, data and peripheral memory spaces must not
//      exceed 64 kB
//

// Program Memory Size:
//                     Uncomment the required memory size
//-------------------------------------------------------
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
//`define PMEM_SIZE_8_KB
//`define PMEM_SIZE_4_KB
`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB


// Data Memory Size:
//                     Uncomment the required memory size
//-------------------------------------------------------
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
//`define DMEM_SIZE_2_KB
//`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B
//`define DMEM_SIZE_256_B
`define DMEM_SIZE_128_B


// Include/Exclude Hardware Multiplier
`define MULTIPLIER


// Include/Exclude Serial Debug interface
`define DBG_EN


The only design considerations at this stage are:
  • Make sure that the program and data memories have the correct size :-P
  • The sum of program, data and peripheral memory space MUST NOT exceed 64 kB

2.1.3.2 Advanced System Configuration

In this section, some additional features are available in order to match the needs of more experienced users.




//============================================================================
//============================================================================
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
//============================================================================
//============================================================================

//-------------------------------------------------------
// Custom user version number
//-------------------------------------------------------
// This 5 bit field can be freely used in order to allow
// custom identification of the system through the debug
// interface.
// (see CPU_ID.USER_VERSION field in the documentation)
//-------------------------------------------------------
`define USER_VERSION 5'b00000


//-------------------------------------------------------
// Include/Exclude Watchdog timer
//-------------------------------------------------------
// When excluded, the following functionality will be
// lost:
//        - Watchog (both interval and watchdog modes)
//        - NMI interrupt edge selection
//        - Possibility to generate a software PUC reset
//-------------------------------------------------------
`define WATCHDOG


///-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI


//-------------------------------------------------------
// Input synchronizers
//-------------------------------------------------------
// In some cases, the asynchronous input ports might
// already be synchronized externally.
// If an extensive CDC design review showed that this
// is really the case,  the individual synchronizers
// can be disabled with the following defines.
//
// Notes:
//        - all three signals are all sampled in the MCLK domain
//
//        - the dbg_en signal reset the debug interface
//         when 0. Therefore make sure it is glitch free.
//
//-------------------------------------------------------
`define SYNC_NMI
//`define SYNC_CPU_EN
//`define SYNC_DBG_EN


//-------------------------------------------------------
// Peripheral Memory Space:
//-------------------------------------------------------
// The original MSP430 architecture map the peripherals
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
// The following defines allow you to expand this space
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
// As a consequence, the data memory mapping will be
// shifted up and a custom linker script will therefore
// be required by the GCC compiler.
//-------------------------------------------------------
//`define PER_SIZE_32_KB
//`define PER_SIZE_16_KB
//`define PER_SIZE_8_KB
//`define PER_SIZE_4_KB
//`define PER_SIZE_2_KB
//`define PER_SIZE_1_KB
`define PER_SIZE_512_B


//-------------------------------------------------------
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
// (CPU break on PUC reset)
//-------------------------------------------------------
// When defined, the CPU will automatically break after
// a PUC occurrence by default. This is typically useful
// when the program memory can only be initialized through
// the serial debug interface.
//-------------------------------------------------------
`define DBG_RST_BRK_EN


Design consideration at this stage are:
  • Setting a peripheral memory space to something else than 512B will shift the data memory mapping up, which in turn will require the use of a custom linker script. If you don't know what a linker script is and if you don't want to know what it is, you should probably not modify this section.
  • The sum of program, data and peripheral memory space MUST NOT exceed 64 kB

2.1.3.3 Expert System Configuration

In this section, you will find configuration options which are relevant for roughly 0.1% of the users (according to a highly reliable market analysis ;-) ).




//============================================================================
//============================================================================
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//============================================================================
//============================================================================
//
// IMPORTANT NOTE:  Please update following configuration options ONLY if
//                 you have a good reason to do so... and if you know what
//                 you are doing :-P
//
//============================================================================

//-------------------------------------------------------
// Number of hardware breakpoint/watchpoint units
// (each unit contains two hardware addresses available
// for breakpoints or watchpoints):
//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//-------------------------------------------------------
// Please keep in mind that hardware breakpoints only
// make sense whenever the program memory is not an SRAM
// (i.e. Flash/OTP/ROM/...) or when you are interested
// in data breakpoints.
//-------------------------------------------------------
//`define  DBG_HWBRK_0
//`define  DBG_HWBRK_1
//`define  DBG_HWBRK_2
//`define  DBG_HWBRK_3


//-------------------------------------------------------
// Enable/Disable the hardware breakpoint RANGE mode
//-------------------------------------------------------
// When enabled this feature allows the hardware breakpoint
// units to stop the cpu whenever an instruction or data
// access lays within an address range.
// Note that this feature is not supported by GDB.
//-------------------------------------------------------
//`define DBG_HWBRK_RANGE


//-------------------------------------------------------
// ASIC version
//-------------------------------------------------------
// When uncommented, this define will enable the
// ASIC system configuration section (see below) and
// will activate scan support for production test.
//
// WARNING: if you target an FPGA, leave this define
//          commented.
//-------------------------------------------------------
//`define ASIC


Design consideration at this stage are:
  • This is the expert section... so you know what your are doing anyway right ;-)

All remaining defines located after the ASIC section in the openMSP430_defines.v file are system constants and MUST NOT be edited.

2.1.4 Memory mapping

As discussed earlier, the openMSP430 memory mapping is fully configurable.
The basic system configuration section allows to adjust program and data memory sizes while keeping 100% compatibility with the pre-existing linker scripts provided by MSPGCC (or any other toolchain for that matter).
However, an increasing number of users saw the 512B space available for peripherals in the standard MSP430 architecture as a limitation. Therefore, the advanced system configuration section gives the possibility to up-scale the reserved peripheral address space anywhere between 512B and 32kB. As a consequence, the data memory space will be shifted up, which means that the linker script of your favorite toolchain will have to be modified accordingly.
The following schematic should hopefully illustrate this:


Memory mapping


2.1.5 Pinout

The full pinout of the openMSP430 core is provided in the following table:

Port Name Direction Width Clock
Domain
 Description
Clocks & Power-Managment
cpu_en Input 1 <async>
or mclk4		 Enable CPU code execution (asynchronous and non-glitchy).
Set to 1 if unused.
dco_clk Input 1 -
 Fast oscillator (fast clock)
lfxt_clk Input
 1
 -
 Low frequency oscillator (typ. 32kHz)
Set to 0 if unused.
mclk Output
 1
 -
 Main system clock
aclk_en Output 1
 mclk
 FPGA ONLY: ACLK enable
smclk_en Output 1
 mclk
 FPGA ONLY: SMCLK enable
dco_enable
 Output
 1
 dco_clk
 ASIC ONLY: Fast oscillator enable
dco_wkup
 Output
 1
 <async>
 ASIC ONLY: Fast oscillator wakeup (asynchronous)
lfxt_enable
 Output
 1
 lfxt_clk
 ASIC ONLY: Low frequency oscillator enable
lfxt_wkup
 Output
 1
 <async>
 ASIC ONLY: Low frequency oscillator wakeup (asynchronous)
aclk
 Output
 1
 -
 ASIC ONLY: ACLK
smclk
 Output
 1
 -
 ASIC ONLY: SMCLK
wkup
 Input
 1
 <async>
 ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
Set to 0 if unused.
Resets
puc_rst Output 1 mclk
 Main system reset
reset_n Input 1 <async>
 Reset Pin (active low, asynchronous and non-glitchy)
Program Memory interface
pmem_addr Output `PMEM_AWIDTH 1 mclk
 Program Memory address
pmem_cen Output 1 mclk
 Program Memory chip enable (low active)
pmem_din Output 16 mclk
 Program Memory data input (optional 2)
pmem_dout Input 16 mclk
 Program Memory data output
pmem_wen Output 2 mclk
 Program Memory write byte enable (low active) (optional 2)
Data Memory interface
dmem_addr Output `DMEM_AWIDTH 1 mclk
 Data Memory address
dmem_cen Output 1 mclk
 Data Memory chip enable (low active)
dmem_din Output 16 mclk
 Data Memory data input
dmem_dout Input 16 mclk
 Data Memory data output
dmem_wen Output 2 mclk
 Data Memory write byte enable (low active)
External Peripherals interface
per_addr Output 14 mclk
 Peripheral address
per_din Output 16 mclk
 Peripheral data input
per_dout Input 16 mclk
 Peripheral data output
per_en Output 1 mclk
 Peripheral enable (high active)
per_we Output 2 mclk
 Peripheral write enable (high active)
Interrupts
irq Input 14 mclk
 Maskable interrupts (one-hot signal)
nmi Input 1 <async>
or mclk4		 Non-maskable interrupt (asynchronous and non-glitchy)
Set to 0 if unused.
irq_acc Output 14 mclk
 Interrupt request accepted (one-hot signal)
Serial Debug interface
dbg_en Input 1 <async>
or mclk4		 Debug interface enable (asynchronous) 3
dbg_freeze Output 1 mclk
 Freeze peripherals
dbg_uart_txd Output 1 mclk
 Debug interface: UART TXD
dbg_uart_rxd Input 1 <async>
 Debug interface: UART RXD (asynchronous)
Scan
scan_enable
 Input
 1
 dco_clk
 ASIC ONLY: Scan enable (active during scan shifting)
scan_mode
 Input
 1
 <stable>
 ASIC ONLY: Scan mode

1: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.
2: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.
3: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the dbg_en port can be used to reset the debug interface without disrupting the CPU execution.
4: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).

Note: in the FPGA configuration, the ASIC ONLY signals must be left unconnected (for the outputs) and tied low (for the inputs).

2.1.6 Instruction Cycles and Lengths

Please note that a detailed description of the instruction and addressing modes can be found in the MSP430x1xx Family User's Guide (Chapter 3).

The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.
In the following tables, the number of clock cycles refers to the main clock (MCLK). Differences with the original MSP430 are highlighted in green (the original value being red).
  • Interrupt and Reset Cycles
Action No. of Cycles Length of Instruction
Return from interrupt (RETI) 5 1
Interrupt accepted 6 -
WDT reset 4 -
Reset (!RST/NMI) 4 -
  • Format-II (Single Operand) Instruction Cycles and Lengths
Addressing Mode No. of Cycles Length of Instruction
RRA, RRC, SWPB, SXT PUSH CALL
Rn 1 3 3 (4) 1
@Rn 3 4 4 1
@Rn+ 3 4 (5) 4 (5) 1
#N N/A 4 5 2
X(Rn) 4 5 5 2
EDE 4 5 5 2
&EDE 4 5 5 2
  • Format-III (Jump) Instruction Cycles and Lengths
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
  • Format-I (Double Operand) Instruction Cycles and Lengths
Addressing Mode No. of Cycles Length of Instruction
Src Dst
Rn Rm 1 1
PC 2 1
x(Rm) 4 2
EDE 4 2
&EDE 4 2
@Rn Rm 2 1
PC 3 (2) 1
x(Rm) 5 2
EDE 5 2
&EDE 5 2
@Rn+ Rm 2 1
PC 3 1
x(Rm) 5 2
EDE 5 2
&EDE 5 2
#N Rm 2 2
PC 3 2
x(Rm) 5 3
EDE 5 3
&EDE 5 3
x(Rn) Rm 3 2
PC 3 (4) 2
x(Rm) 6 3
EDE 6 3
&EDE 6 3
EDE Rm 3 2
PC 3 (4) 2
x(Rm) 6 3
EDE 6 3
&EDE 6 3
&EDE Rm 3 2
PC 3 2
x(Rm) 6 3
EDE 6 3
&EDE 6 3

2.1.7 Serial Debug Interface

All the details about the Serial Debug Interface are located here.

2.2 System Peripherals

In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration. The followings are directly integrated within the core because of their tight links with the CPU.
It is to be noted that ALL system peripherals support both ASIC and FPGA versions.

2.2.1 Basic Clock Module: FPGA

In order to make an FPGA implementation as simple as possible (ideally, a non-professional designer should be able to do it), clock gates are not used in this design configuration and neither are clock muxes.
With these constrains, the Basic Clock Module is implemented as following:

Clock structure diagram
Note: CPUOFF doesn't switch MCLK off and will instead bring the CPU state machines in an IDLE state while MCLK will still be running.

In order to 'clock' a register with ACLK or SMCLK, the following structure needs to be implemented:

Clock implementation example

For example, the following Verilog code would implement a counter clocked with SMCLK:



reg [7:0] test_cnt;

always @ (posedge mclk or posedge puc_rst)
if (puc_rst) test_cnt <= 8'h00;
else if (smclk_en) test_cnt <= test_cnt + 8'h01;


Register Description
  • DCOCTL: Not implemented
  • BCSCTL1:
    • BCSCTL1[7:6]: Unused
    • BCSCTL1[5:4]: DIVAx
    • BCSCTL1[4:0]: Unused
  • BCSCTL2:
    • BCSCTL2[7:4]: Unused
    • BCSCTL2[3]   : SELS
    • BCSCTL2[2:1]: DIVSx
    • BCSCTL2[0]   : Unused

2.2.2 Basic Clock Module: ASIC

When targeting an ASIC, up to all clock management options available in the MSP430x1xx Family User's Guide (Chapter 4) can be included:

Clock structure diagram
Additional info can be found in the ASIC implementation section.

2.2.3 SFR

Following the MSP430x1xx Family User's Guide, this peripheral implements flags and interrupt enable bits for the Watchdog Timer and NMI:

Register Name Address Bit Fields
7
 6
 5
 4
 3
 2
 1
 0
IE1
 0x0000  Reserved
NMIIE 1   Reserved  WDTIE 2
IFG1
 0x0002 Reserved
 NMIIFG 1 Reserved WDTIFG 2

1: These fields are not available if the NMI is excluded (see openMSP430_defines.v )
2: These fields are not available if the Watchdog is excluded (see openMSP430_defines.v )

In addition, two 16-bit read-only registers have been added in order to let the software know with which version of the openMSP430 it is running:

Register Name Address Bit Field
1514 1312 1110 9 8 7 6 5 4 3 2 1 0
CPU_ID_LO 0x0004 PER_SPACE USER_VERSION ASIC CPU_VERSION
CPU_ID_HI 0x0006 PMEM_SIZE DMEM_SIZE MPY

 
  • CPU_VERSION
    		•  : Current CPU version
     
  • ASIC
    		•  : Defines if the ASIC specific features are enabled in the current openMSP430 implementation.
     
  • USER_VERSION
    		•  : Reflects the value defined in the openMSP430_defines.v file.
     
  • PER_SPACE
    		•  : Peripheral address space for the current implementation (byte size = PER_SPACE*512)
     
  • MPY
    		•  : This bit is set if the hardware multiplier is included in the current implementation
     
  • DMEM_SIZE
    		•  : Data memory size for the current implementation (byte size = DMEM_SIZE*128)
     
  • PMEM_SIZE
    		•  : Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)

    Note: attentive readers will have noted that CPU_ID_LO and CPU_ID_HI are identical to the Serial Debug Interface register counterparts.

    2.2.4 Watchdog Timer

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 10) have been implemented.

    The following parameter in the openMSP430_defines.v file controls if the watchdog timer should be included or not:

    		//-------------------------------------------------------
    // Include/Exclude Watchdog timer
    //-------------------------------------------------------
    // When excluded, the following functionality will be
    // lost:
    //        - Watchog (both interval and watchdog modes)
    //        - NMI interrupt edge selection
    //        - Possibility to generate a software PUC reset
    //-------------------------------------------------------
    `define WATCHDOG

    2.2.5 16x16 Hardware Multiplier

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 7) have been implemented.

    The following parameter in the openMSP430_defines.v file controls if the hardware multiplier should be included or not:

    		// Include/Exclude Hardware Multiplier
    `define MULTIPLIER

    2.3 External Peripherals

    The external peripherals labeld with the "FPGA ONLY" tag do not contain any clock gate nor clock muxes and are clocked with MCLK only. This mean that they don't support any of the low power modes and therefore are most likely not suited for an ASIC implementation.

    2.3.1 Digital I/O (FPGA ONLY)

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 9) have been implemented.

    The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):




    		parameter P1_EN = 1'b1; // Enable Port 1
    parameter P2_EN = 1'b1; // Enable Port 2
    parameter P3_EN = 1'b0; // Enable Port 3
    parameter P4_EN = 1'b0; // Enable Port 4
    parameter P5_EN = 1'b0; // Enable Port 5
    parameter P6_EN = 1'b0; // Enable Port 6

    They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):




    		gpio #(.P1_EN(1),
    .P2_EN(1),
    .P3_EN(1),
    .P4_EN(0),
    .P5_EN(0),
    .P6_EN(0)) gpio_0 (

    The full pinout of the GPIO module is provided in the following table:

    Port Name Direction Width Description
    Clocks & Resets
    mclk Input 1 Main system clock
    puc_rst Input 1 Main system reset
    Interrupts
    irq_port1 Output 1 Port 1 interrupt
    irq_port2 Output 1 Port 2 interrupt
    External Peripherals interface
    per_addr Input 8 Peripheral address
    per_din Input 16 Peripheral data input
    per_dout Output 16 Peripheral data output
    per_en Input 1 Peripheral enable (high active)
    per_wen Input 2 Peripheral write enable (high active)
    Port 1
    p1_din Input 8 Port 1 data input
    p1_dout Output 8 Port 1 data output
    p1_dout_en Output 8 Port 1 data output enable
    p1_sel Output 8 Port 1 function select
    Port 2
    p2_din Input 8 Port 2 data input
    p2_dout Output 8 Port 2 data output
    p2_dout_en Output 8 Port 2 data output enable
    p2_sel Output 8 Port 2 function select
    Port 3
    p3_din Input 8 Port 3 data input
    p3_dout Output 8 Port 3 data output
    p3_dout_en Output 8 Port 3 data output enable
    p3_sel Output 8 Port 3 function select
    Port 4
    p4_din Input 8 Port 4 data input
    p4_dout Output 8 Port 4 data output
    p4_dout_en Output 8 Port 4 data output enable
    p4_sel Output 8 Port 4 function select
    Port 5
    p5_din Input 8 Port 5 data input
    p5_dout Output 8 Port 5 data output
    p5_dout_en Output 8 Port 5 data output enable
    p5_sel Output 8 Port 5 function select
    Port 6
    p6_din Input 8 Port 6 data input
    p6_dout Output 8 Port 6 data output
    p6_dout_en Output 8 Port 6 data output enable
    p6_sel Output 8 Port 6 function select

    2.3.2 Timer A (FPGA ONLY)

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 11) have been implem

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