4-way set associative level 2 unified cache for NIOS II/e, SOPC builder compatible :: Overview

Project maintainers


Name: level2_cache_nios_iie
Created: Jun 28, 2011
Updated: Aug 19, 2012
SVN: No files checked in

Other project properties

Category: Memory core
Language: Verilog & VHDL
Development status: Stable
Additional info: none
WishBone Compliant: No
License: LGPL


This project is an implementation of a unified L2-cache for a NIOS II/e processor. The cache is located between the Avalon bus and the SDRAM controller.

Key features are:
- 4-way set associative
- 8KB cache size (2KB per way)
- Up to 128MB of cached memory (limited by the 18-bit tags)
- 32-bit data bus on the Avalon bus side, 16-bit data bus on the SDRAM controller side
- 16-byte cache lines (8-word burst on the SDRAM side)
- Cache can be used as a 8KB boot ROM during startup

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