部分翻译
Request(s)
| Date |
Title |
Status |
Assigned to |
Submitted by |
| Nov 9, 2011 |
how to initialize i2c_busy |
OPENED |
|
wojtAS |
| Oct 24, 2011 |
|
OPENED |
|
vickyxia |
| Sep 30, 2010 |
Documentation of VHDL for output buffers |
CLOSED |
|
Schwirz |
| Aug 30, 2010 |
Arbitration lost |
OPENED |
|
cheevu |
| Jul 1, 2010 |
sequence to read RxAck from status register |
OPENED |
|
allamovich_1 |
| Jul 1, 2010 |
how to read from status register |
CLOSED |
|
allamovich_1 |
| May 4, 2010 |
Slave mode |
OPENED |
|
janoukie |
| Sep 3, 2009 |
Arbitration problem |
CLOSED |
rherveille |
pignoffo |
| Jul 10, 2009 |
The core DO NOT support large i2c slave? |
CLOSED |
|
markman |
| Jun 6, 2009 |
I2C core and Max Wishbone frequency |
CLOSED |
|
gerry |
Bug(s)
| Date |
Title |
Status |
Assigned to |
Submitted by |
| Nov 23, 2011 |
|
CLOSED |
|
pipidu |
| Jun 8, 2011 |
i2c_slave_model is not a synthesizable code |
CLOSED |
|
jerry_hsu |
| Jun 8, 2011 |
i2c_slave_model invalid slave address will issue a error write |
OPENED |
|
jerry_hsu |
| Dec 4, 2010 |
bit_controller state machine o/ps |
CLOSED |
|
pranavverma |
| Aug 6, 2010 |
Presacler or Documentation wrong |
OPENED |
|
but5693 |
| May 31, 2010 |
Init filter_cnt |
CLOSED |
rherveille |
jon_vdb |
| Mar 5, 2010 |
wrong copy/paste |
CLOSED |
rherveille |
cbeguet |
| Mar 4, 2010 |
Missing Library |
OPENED |
|
cbeguet |
| Jul 3, 2009 |
blocking and non-blocking |
CLOSED |
rherveille |
markman |
| Jun 1, 2009 |
WISHBONE Bus captures write data twice. |
CLOSED |
rherveille |
rehayes |
| Apr 30, 2009 |
extra SCL tick |
OPENED |
rherveille |
stustuff123 |
| Feb 12, 2009 |
Arbitration error in (vhdl) version 1.17 of the i2c_master_bit_ctrl |
CLOSED |
rherveille |
awijsmuller |
| Jan 29, 2009 |
project lists under VHDL ...but no VHDL |
DELETED |
rherveille |
poppafuze |
| Jan 20, 2009 |
scl_oen? |
DELETED |
rherveille |
olaf.vandenberg |
| Nov 3, 2008 |
Strange I2C behavior (reads->writes) |
CLOSED |
rherveille |
galland |
| Aug 9, 2008 |
Repeated Start Tsu |
OPENED |
rherveille |
vackovik@yahoo.com |
| Jul 26, 2008 |
Clock synchronization for multi-master system |
CLOSED |
rherveille |
ivanlawrow@yahoo.com |
| Apr 9, 2008 |
Lacking example and erroneous example? |
CLOSED |
|
wzab@ise.pw.edu.pl |
| May 25, 2007 |
START doesn't satisfy Timing Requirements? |
CLOSED |
rherveille |
jeremy.hannon@ge.com |
| Aug 4, 2004 |
testbench error |
CLOSED |
rherveille |
kelvin_bao@163.com |
| Feb 10, 2004 |
Testbench error |
CLOSED |
rherveille |
martin.j.thompson@trw.com |
Idea(s)
Reminder(s)
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