Hardware Assisted IEEE 1588 IP Core :: Overview
Project maintainers
Details
Name: ha1588
Created: Mar 6, 2012
Updated: Feb 12, 2013
SVN Updated: Feb 6, 2013
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Latest version: download
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Other project properties
Category: Communication controller
Language: Verilog
Development status: Beta
Additional info:
Design done, Specification done
WishBone Compliant: Yes
License: LGPL
Description
Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with any existing MAC function internal or external to the FPGA; This IP Core implements the Real-Time Clock (RTC) and Time Stamping of PTP event packets (TSU).
Feature Description
RTC: Real Time Clock.
* Standard PTP clock output with 2^48s and 2^32ns time format.
* 1PPS output for clock accuracy measurement.
* Tunable accumulator based clock with 2^-8ns time resolution and 2^-32ns period resolution.
** Direct time write, with 2^-8ns resolution.
** Direct frequency write, with 2^-32ns resolution.
** Timed temporary time adjustment, with 2^-8ns resolution and 32bit timer.
* Variable input clock frequency.
* Clock Domain Crossing hand-shaking, for SW read and write access.
TSU: Time Stamping Unit.
* Two-Step PTP operation.
* GMII/MII interface monitor with line-speed PTP packet parsing.
* Variety of PTP packet formats supported.
** IEEE 802.3 L2 PTP packet, with stacked VLAN tags.
** IPv4/UDP and IPv6/UDP L4 PTP packet, with stacked VLAN tags and/or stacked MPLS labels.
* Configurable 8bit mask to selectively timestamp PTP event packet based on message type value.
** 0: Sync
** 1: Delay_Req
** 2: Pdelay_Req
** 3: Pdelay_Resp
** 4 to 7: Reserved for future PTP event message types
* 32bit packet parser datapath for easier timing closure.
* 15-entry timestamp queue.
* 128bit timestamp format.
** 16bit extra information.
** 80bit timestamp.
** 32bit packet identity data.
SystemVerilog DPI based simulation environment is included for SW driver development and co-simulation.
PCAP file based stimulus input is included for verification with real-world traffic.
The IP Core can be used as an IP Component in Altera Qsys, Xilinx XPS or WishBone.
The only FPGA vendor dependent module is the timestamp queue. This Altera DCFIFO can be replaced by any equivalent dual clock FIFO from other FPGA vendors.