a VHDL 16550 UART core :: Bugtracker
Request(s)
| Date | Title | Status | Assigned to | Submitted by |
| Nov 5, 2010 | UART and gh_baud_rate_gen | CLOSED | hlefevre | cbeguet |
Bug(s)
| Date | Title | Status | Assigned to | Submitted by |
| Dec 8, 2010 | Xilinx iSim generates "out of valid range" error | OPENED | c.noble | |
| Jul 6, 2009 | CS in APB Wrapper | CLOSED | hlefevre | cbeguet |
| Jul 21, 2008 | Break state persists after condition cleared | CLOSED | hlefevre | nzeitler@osii.com |
| Jun 18, 2008 | Transmit Interrupt doesn't fire during a Single Byte Send | CLOSED | hlefevre | auchter@uwalumni.com |
| Oct 11, 2007 | Clearing Receiver Line Status Interrupt | CLOSED | hlefevre | mklemm@dspace.de |
| Oct 10, 2007 | Enabling THRE Interrupt | CLOSED | hlefevre | djj08230@gmail.com |
| Aug 6, 2007 | Fifos' reset doesn't work | CLOSED | hlefevre | astenu@wp.pl |
| Aug 6, 2007 | Fifos' reset doesn't work | CLOSED | hlefevre | astenu@wp.pl |
| Aug 2, 2007 | Timeout interrupt | CLOSED | hlefevre | astenu@wp.pl |
| Oct 12, 2006 | Clock configuration is wrong | CLOSED | hlefevre | dmarris@charter.net |