Overview

Details

Name: or1k
Created: Sep 25, 2001
Updated: Feb 7, 2012
SVN Updated: Feb 24, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License: LGPL

Introduction

The aim of the OpenRISC project is to create free and open source computing platforms available under the GNU (L)GPL license. The platforms aim to provide:

a free, open source RISC architecture with DSP features
a set of free, open source implementations of the architecture
a complete set of free, open source software development tools, libraries, operating systems and applications

The architecture specifications are published under the GNU GPL. Third parties are permitted to create their own proprietary processor implementations. It is also possible to port proprietary software to the OpenRISC platform. Use and development of the implementations and software provided by the project is encouraged.

The OpenRISC 1000 architecture is the first set of specifications for a family of 32- and 64-bit RISC/DSP processors. Its open and modular architecture allows a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. Designed with emphasis on performance, simplicity, low power consumption, scalability and versatile implementation, it targets medium and high performance networking, portable, embedded, and automotive applications.

News

See the news page for the latest developments. Announcements also occur in the OpenRISC forum.

Wishlist (TODO List)

If you would like to help with the development, please post to the OpenRISC forum or send an email to openrisc_team@opencores.org.

1. Linux 2.6 port testing
2. More ORPSoC board implementations.
3. Demo Applications using OpenRISC Technology
4. Ports of Commercial Software Development Tools
5. Ports of Commercial Operating Systems (including RTOSes)
6. Port/Optimization of various DSP libraries (G.7xx codecs etc.)
7. RedHat eCos Port

If you have a suggestion for new Wishlist entry, feel free to send it to openrisc_team@opencores.org.

Project Maintainers

This project is maintained by

Past Contributor(s)

These are the people currently not working on the OpenRISC, but have contributed allot in the past:

Damjan Lampret, Johan Rydberg, Chen-Min Chen, Greg McGary, Chris Ziomkowsi, Marko Mlinar, Simon Srot, Matan Ziv-Av, Balint Cristian, Matjaz Breskvar, and many more.....

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