OpenCores

OR1200 OpenRISC processor

Introduction

The aim of this project is to design and maintain an OpenRISC 1200 IP Core. OpenRISC 1200 is an implementation of OpenRISC 1000 processor family.

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.

OR1200 overview

Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.

By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.

Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.

When implemented in a worst-case 0.18u 6LM process it should provide over 150 dhrystone 2.1 MIPS at 150MHz and 150 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class (typical corner 250MHz).

The default OR1200 configuration is about 40k ASIC gates.

General Microarchitecture

  • Central CPU/DSP block
  • IEEE 754 compliant single precision FPU
  • Direct mapped data cache
  • Direct mapped instruction cache
  • Data MMU based on hash-based DTLB
  • Instruction MMU based on hash-based ITLB
  • Power management unit and power management interface
  • Tick timer
  • Debug unit and development interface
  • Interrupt controller and interrupt interface
  • Instruction and Data WISHBONE B3 compliant interfaces

Status

RTL coding is finished and is being tested in different test applications. It has also been implemented in various commersial ASICs and FPGA.

If you would like to help with the development, please post to the OpenRISC forum or send an email to openrisc_team@opencores.org.

Downloading OR1200 processor

We recommend you checkout the latest (development) version from SVN using:

svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1200

Older versions are located in the TAGS directory.

The configuration of the processor when checked out from the repository (defined by the or1200_defines.v file) is currently:

  • FPGA targeted
  • Generic technology targeted
  • Instruction cache enabled, 8kByte
  • Data cache enabled, write-through, 8kByte
  • Instruction MMU enabled
  • Data MMU enabled
  • Hardware multiplication/division enabled
  • Single precision floating point unit disabled
  • Wishbone bus (rev. B3 compatible) bursting enabled
  • Debug unit enabled
  • Boot address at 0x00000100, EPH not set (exceptions at 0x0)

Note: the configuration of the processor in the repository is subject to change. Be sure to check the or1200_defines.v carefully file before use.

Implementation information

Default configuration

  • 15K core cells (1850 FFs, 48 block RAMs) at 25MHz on Actel ProASIC3 technology
  • 4K LUTs, 7 block RAM at 60MHz on Xilinx Virtex 5 technology

ORPSoC implementation performance statics (benchmarks run within ORPmon):

OR1200, 8KByte/4KByte I/D cache, hardware multiply/divide disabled, @20MHz on Actel ProASIC3, SDR SDRAM

  • Dhrystone (120,000 runs): 17,000 Dhrystones/second
  • CoreMark 1.0 : 11.954573 (0.6 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O2 -msoft-mul -msoft-div -msoft-float / STACK

OR1200, 8KByte/4KByte I/D cache, hardware multiply/divide enabled, @20MHz on Actel ProASIC3, SDR SDRAM

  • Dhrystone (120,000 runs): 20,000 Dhrystones/second
  • CoreMark 1.0 : 25.773196 (1.25 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O2 -mhard-mul -mhard-div -msoft-float / STACK

OR1200, 32KByte/32KByte I/D cache, hardware multiply/divide enabled, @50MHz on Xilinx ML501

  • Dhrystone (500,000 runs): 50,000 Dhrystones/second
  • CoreMark 1.0 : 66.788100 (1.34 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O3 -mhard-mul -mhard-div -msoft-float -nostdlib / STACK

Minimal configuration

  • 7K core cells (1100 FFs, 4 block RAMs) at 35MHz on Actel ProASIC3 technology
  • 2.4K LUTs, 1 block RAM at 125MHz on Xilinx Virtex 5 technology

Documentation

Specification document for OpenRISC 1200 is available in Adobe PDF, MS Word, and Open Office formats:

A Japanese translation of the specification by Takashi Okawa is available from the Downloads page.

Also see the architecture page for the OpenRISC 1000 family.

Tutorials are available on how to implement OR1200 on Altera FPGA and Xilinx FPGA. Credits go to Resarch Group Digital Techniques, Hogeschool voor Wetenschap & Kunst, Campus de Nayer:

Wish List (TODO List)

This is what we would like to develop/see developed but presently nobody is working on these projects. If you want to help, send an email to openrisc_team@opencores.org.

  • Bring OR1200 specification document into line with what is actually in the RTL. A few sections still need going over (debug interface, for one.)
  • Add multiple associativity to cache and MMU
  • Optimize for speed, area and power
  • Test OR1200 in your applications
  • Write design document

Wish List suggestions can be posted on the OpenRISC Forum.

Discussion Forum

To participate in the development or simply to discuss OpenRISC 1200 issues, go to the OpenRISC forum.

Please report any bugs using the OpenRISC Bug Tracker.

Page Maintainer

This web page is maintained by

  • Marcus Erlandsson
  • Michael Unneback
  • Julius Baxter
Top
© copyright 1999-2012 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.