OpenRISC development board from ORSoC

System-on-Module update

Update about the new System-on-Module that is currently under development.


Graphics Accelerator

A graphics accelerator IP Core that can handle 2D, vector and some basic 3D graphics.


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
This month: 7 new projects


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Newsletter May 2012

System-on-Module updates

For an upcoming System-on-Module design we are evaluating an EDA tool from Altium called Designer. If you missed the previous information about this "System-on-Module", it can be found here.
Altium Designer is a tool suite targeted for FPGA centric designs and therefor has the possibility to be a very useful tool. This design has many of the design challenges normally found when designing system around FPGAs:

1. High speed differential signals (in this case USB2.0, Ethernet and SERDES lines from the Cyclone IV GX)
2. Length tuning of clock signals (in this case for the memory system)
3. Pin swapping in FPGA IO banks (in this case for FPGA IO, FLASH memory and PCI)
4. Defining symbols for high pin count devices (in this case ALTERA Cyclone IV GX)

In Altium Designer there are functions for developing your FPGA design including a C to hardware function. We have not looked on those features yet. This evaluation has been for the Schematic editor and PCB layout tool.

Based on our experience with the design of a System-on-Module, we will go through the design challenges mentioned above.

High speed differential signals
Differential signals can be defined in the schematic editor by placing a tag related to the wire pair. The naming of the signals must have a suffix of _P and _N to identify the wire pair. This will propagate to the PCB tool. You can route the pair with an interactive router. It is important to have a correct stack-up layer defined for the PCB otherwise the impedance will not be correct. In the tool there is also a signal integrity simulator based on IBIS models. We have not yet used this.

Length tuning
In this design the clock traces for the SDRAM going to the memory and back to the SoC shall have equal length. This is accomplished with the interactive length tuning router in Altium Designer. Before routing you define what type of trace patterns the tool shall include. Interactively route the shortest trace with the length tuning turned on until the trace length matches.

Pin swapping
For this design the largest number of IO connections are for the IO signals in the SO-DIMM connector and the PCI connections towards the SoC device. In Altium Designer signals on a symbol can be defined in groups. In this case we created one group for the IO signals and an other for the PCI signals. You can swap IO signals to automatically achieve shortest distance or using an interactive swap function. We used the later alternative. With this strategy it was possible to route the majority of the PCI signals using one single layer on the board.

Schematic symbols
For ALTERA, Xilinx, Actel and Lattice symbols for FPGA are already defined and available in the tool. This simplifies design and help you avoiding problems.

We believe Altium Designer is a very competitive tool meeting many of today design challenges. And doing so at a very affordable pricing. More information regarding the tool can be found at Altiums website

Michael Unnebäck, ORSoC

Graphic Accelerator

The ORSoC Graphics Accelerator, “ORGFX” for short, is a graphics accelerator IP Core that can handle 2D, vector and some basic 3D graphics. The ORGFX is platform independent and is easy to add to current projects. ORGFX have three wishbone interfaces, one connects to a databus for the host controller while the other two connects to video memory.

The ORSoC Graphics Accelerator can:
- Draw Lines.
- Draw Filled or Textured Rectangles.
- Draw Filled, Interpolated or Textured Triangles.
- Draw Filled Quadratic Bézier Curves.
- Write Text with Bitmap Fonts or Vector Fonts.
- Draw Alphablended shapes.
- Draw Colorkeyed images.
- Draw 3D meshes with support for depth buffer.
- Transform points (scaling & rotation of triangles and vector fonts).

ORSoC GFX comes with a set of conversion utilities to easily incorporate standard graphic formats into the supplied software drivers.

The ORSoC GFX utilities supports the following file formats:
- TrueType fonts (.ttf) for vector fonts.
- Wavefront .OBJ files for 3D meshes (including textures).
- Common image formats for sprites and textures: .bmp, .png, .jpg, etc. (all formats supported by SDL_image).

The project is available for download at: OpenCores.

There is an example implementation based on the OpenRISC processor available. A YouTube video showing some of the features of the ORGFX can be found here.

Think the project sounds interesting but don’t have the FPGA hardware to run it? The project comes with a software implementation using SDL to emulate all functions of the graphics accelerator. Programs written for the emulator works on the FPGA without any modifications.

Per Lenander and Anton Fosselius are two students from Mälardalen University in Sweden that have been working on this project for their thesis work during the spring, the project was intitiated by ORSoC. If you have any questions please contact them at: or

/Anton & Per

Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Running smoothly

Server information:

  • Running smoothly.

Our message to the community:

  • Help us improve the community, please provide feedback

Marcus Erlandsson, ORSoC

New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

RC4 Pseudo-random stream generator
RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then start outputting one-byte of stream for every clock. Based on RC4 implementation in wikipedia.

Development status: Beta
License: LGPL
May 21, 2012: Updated licensing to LGPL
May 18, 2012: First version - RC4 algorithm working but need modularization

Polyphase Decimation Filter
This is a behavioral SystemC model for Polyphase Decimation filters. It can be used as for system design and functional verification. It has been tested with Matlab and Octave as well. If you need any further illustrations or further modifications, don't hesitate to contact me. It can be used effectively for class instruction. It is a good practice for SystemC beginners and DSP student/engineers as well.
Development status: Stable
License: LGPL
May 11, 2012: uploaded

PSG16 - ADSR prog. sound gen.
PSG16 is an audio interface circuit for use within a programmable system to interface the system to an audio output. It supports four ADSR audio channels with a wavetable option.

- four ADSR / wave table channels
- programmable frequency and pulse width control
- 0.06 Hz frequency resolution
- attack, decay, sustain and release
- test, ringmod, sync and gate controls
- five voice types: triangle, square, pulse, noise and wave
- exponential decay and release

Development status: Planning
License: LGPL
May 28, 2012: Updated project description, adding files

System-on-Module based on an ARM SoC in combination with an ALTERA FPGA. Focus for this module is connectivity, flexibility and a high performance/price ratio.

Form factor
The form factor for this module is 200 pin SO-DIMM.

Module has a rich flavor of connectivity available.
The ARM SoC from Micrel contains a manageable 4+1 port 10/100 Mbps switch. The switch has built-in Fast Ethernet PHY for this. Two port can optionally support 100FX. The swicth can be used in scenarios with 1 WAN port and 4 LAN ports.
Connected over the KSZ8095P PCI bus is a USB hub with 5 hi-speed USB2.0 compliant ports. Device contains PHY for these channels.
From the FPGA four full duplex SERDES channels are available. These are fully configurable and can optionally support PCI express.

A total of 48 IO signals are available on the edge connector. Out of these 22 signals have configurable IO levels.
The on board ALTERA FPGA can be used for a wide variety of functions including:
- peripherals (UARTs, I2C, SPI, I2S, AC'97, LPC ...)
- coprocessor (connected over PCI sharing main memory with ARM CPU)
- DSP functions (FFT, IIR and FIR filter ...)
- Crypto (MD5, AES, 3DES ...)
Development status: Planning
License: LGPL
May 29, 2012: Length tuning
May 25, 2012: Routing of SoC - FPGA signals completed
May 23, 2012: Pin/Nets swapping
May 21, 2012: routing started
May 14, 2012: schematic 99% finished
May 8, 2012: Updated the description
May 7, 2012: Design blogg kick off
May 7, 2012: Updated description

Johan Rilegård, ORSoC

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