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NEWSLETTER APRIL 2012

OpenRISC development board from ORSoC

Open RVC-CAL Compiler

generate code for any platform, including hardware (VHDL, Verilog), software (C, Java, etc), and heterogeneous platforms (mixed hardware/software) from a platform-agnostic, high-level design.

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Get C directly to silicon

The startup company Algotochip in Silicon Valley has the ambition to change the approach in the design of digital circuits.

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Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

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New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
This month: 7 new projects

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Newsletter March 2012


Open RVC-CAL Compiler

The CAL Actor Language was developed in 2001 as part of the Ptolemy II project at University of California at Berkeley. CAL is a dataflow language geared towards a variety of application domains, such as multimedia processing, control systems, network processing etc. A CAL dataflow program provides simple, understandable, and powerful abstractions that allow the specification of as much or as little parallelism as is required, enabling tools to produce sophisticated implementations that exploit the concurrent structure of a computation.

The Open RVC-CAL Compiler (Orcc) is a compiler under BSD license for the RVC-CAL dataflow programming language. Please consult the project homepage at http://orcc.sourceforge.net for more information.

The Open RVC-CAL Compiler (Orcc) can generate code for any platform, including hardware (VHDL, Verilog), software (C, Java, etc), and heterogeneous platforms (mixed hardware/software) from a platform-agnostic, high-level design.

The Orcc project also provides a dedicated Virtual Machine, the Just-in-time Adaptive Decoder Engine (Jade) based on LLVM infrastructure, that can dynamically produce machine code for a wide range of software platforms.

Michael Unnebäck, ORSoC



Get C directly to silicon

Globalpress: The startup company Algotochip in Silicon Valley has the ambition to change the approach in the design of digital circuits. The company claims that they, based on C code, can create an optimal and energy-efficient digital implementation in only 8 to 16 weeks. An initial design has already been done.

Algotochips business can be summarized in three words "C to silicon," as the company present it.

- We can move a design from algorithm to chip in just eight weeks. We do this by creating a suitable RTL code generated from C code for system-on-silicon (SOC), says Satish Padmanabhan, CTO Algotochip, whose EDA tools is claimed to provide all necessary software, hardware and firmware based C code and test vectors.

Satish Padmanabhan is the man behind Algotochip. Previously, he has been working as the chief architect at ZPS, where he created the first superscalar digital signal processor. Two years ago he founded Algotochip, and he has recruited software experts from Apple and elsewhere.

To date, the company can just give an example of one customer who use its design methodology. The German Mimoon who designed a product, called LTE UE PH, using Algotochip

- Making an LTE solution was probably the most difficult challenge we could take and it has gone well. We are currently working also with a handful of designers who will be announced during the next quarter, says Satish Padmanabhan.

The circuit to Mimoon was initially made in both a 90 nm and 40 nm process at TSMC, but the choice finally fell on the 90nm alternative.

Important to note is that the customer owns the design, says Algotochip. The resulting GDSII design (Graphic Data System II) - from which an EDA system creates the file that is then sent to TSMC for example - and all IPs are owned then by the customer.

- If someone wants to use a licensed core from Arm for example that's fine, but any analog block is something that the customer has to provide himself, says Satish Padmanabhan.

Algotochip also claim that their architecture has good control of leakage currents and to work with other technologies in addition to SoC, such as DSP, asic, ASSP and soon FPGA.

Published by Elektroniktidningen at link



Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Fixed some minor php-bugs.

Server information:

  • Running smoothly.

Our message to the community:

  • The OpenRISC board with expansion connectors are back in stock again

Marcus Erlandsson, ORSoC





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

8-bit uP
This is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible computer. It very useful design which introduces most of the basic and fundamental ideas behind computer operation.

This design could be used for instruction classes for undergraduate classes or specific VHDL classes. This processor is based on the 8080 architecture, therefore, it could be upgraded step by step to integrate further facilities. It is very exciting challenge for the students to do so. Further, they could think about building complete system, i.e. integrating and I/O peripherals to the processor.

The design is proven for ASIC and FPGA. It was implemented using Xilinx FPGA Spartan-3E starter kit. A full documentation for the code and the used resources are attached within the project.

Development status: Stable
License: GPL
Updates:
Apr 11, 2012: Organizing the project
Apr 11, 2012: Preparing a README file

Tiny Tate Bilinear Pairing
This is the same functionality as Tate Bilinear Pairing core @ opencores. But this core uses less hardware resource.
Development status: Alpha
License: LGPL
Updates:
Apr 23, 2012: update information @ webpage

Uart block
Simple uart core with wishbone slave interface and programmable baud rate generator, based on clock speed and desired baud rate
Development status: Planning
License: LGPL
Updates:
Apr 21, 2012: Working on description
Apr 20, 2012: Starting project (Unsigned division block to calculate baudrate)

FIR TF DF
FIR, or Finite Impulse Response, filters have the distinctive trait that their impulse response lasts for a finite duration of time as opposed to IIR, or Infinite Impulse Response, filters whose impulse response is infinite in duration.

Specifications

- as much as 256 TAPs in Xilinx Virtex/Spartan2 (per cascade unit)
- low gate count (on expense of lower input sample frequency range) with a single MAC unit per core and sequential calculation of output samples (TAPs don't operate in parallel)
- 2 to 256 TAPs range set by a user
- 16 bit or less input sample width set by a user
- 16 bit or less coefficient width set by a user
- simple design that allows cascading several FIR filter cores (external adder required)

Development status: Stable
License: GPL
Updates:

G-FIR TF/DF
This is an elementary generic structural VHDL code for FIR digital filters in transposed-form and direct-form implementations.
This project covers a wide spectrum of design aspects, in particular design and both functional and formal verification.
The project is developed in VHDL and modeled in SystemC. The SystemC model is used for functional and formal verification.
TCL scripts for GHDL and SystemC is included within the project files.

This code could be considered for VHDL classes or DSP classes for amateurs or beginners.
The developed code was synthesized for FPGA and ASIC (0.13um CMOS) using:
- Xilinx ISE
- Synopsys Design Compiler
- Cadende RTL Encounter

Further, it was implemented using Xilinx Spartan-3E FPGA utilizing the Spartan-3E Starter Kit. It was tested using Xilinx ChipScope and a complete lab setup, as well. The filter output was converted to analog output using the on-board DAC to trace it on a Spectrum analyser.
Development status: Stable
License: GPL
Updates:
Apr 13, 2012: uploading project

AISystem
The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time celullar and sub-cellular biological processes.
Development status: Alpha
License: Other
Updates:
Mar 31, 2012: License model changed

ULA chip for ZX Spectrum
This is an implementation of the Sinclair ULA chip, found in ZX Spectrum microcomputers. The project offers various implementations: both FPGA friendly (with separate input and output data buses), and CPLD ready, to be used as a replacement for the many chips that comprise the ULA found in some clones.

This project is mostly based upon the work of Chris Smith. Chris designed a ZX Spectrum clon, the "Harlequin". A PCB has been developed by Don "Superfo", which uses discrete logic to implement the ULA, as Chris did. The CPLD version of this implementation is aimed to serve as replacement for that clone.

The ULA implementation follows, where possible, the original ULA timmings, as stated in "The ZX Spectrum ULA: how to design a microcomputer", written by Chris Smith and published by ZX Design and Media, ISBN 978-0-9565071-0-5

There are implementations with some enhancements such as Timex hicolour support and ULA+ support.
Development status: Planning
License: GPL
Updates:
Apr 23, 2012: Updated project description


Johan Rilegård, ORSoC


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