OpenCores

OpenCores.org

NEWSLETTER MARCH 2012

OpenCores AD

The New OpenRISC FPGA board is now back in stock again

More OpenRISC FPGA development boards with expansion connectors have been produced and are now available again in OpenCores webshop.

Read more...


System-on-Module

Based on an ARM SoC and an ALTERA FPGA. Support higher performance and flexibility and still use existing IP-cores from OpenCores.

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
This month: 7 new peojects

Read more...

Banner advertise at OpenCores

OpenCores is the world's largest site/community focusing on open source hardware IP core development.

OpenCores Newsletter is published once a month - it gives you the latest news and updates at the site/community.

Do you wish to unsubscribe from this newsletter - uncheck the subscription button in your account settings at OpenCores. Or do a reply with the text "unsubscribe" in the subject-field.

(c) Copyright Opencores.org, equivalent to ORSoC AB. All rights reserved. OpenCores®, registered trademark.



Newsletter March 2012


The New OpenRISC FPGA board is now back in stock again

The OpenRISC development board with additional expansion connectors was quickly sold out. More boards have been produced and are now available again to buy via OpenCores webshop

We would like to thank the community for all encouraging feedback we received about this board, and of course thanks for all the help with verifying and correcting bugs etc.
We plan to update the VirtualBox-image shortly with some upgrades, so stay tuned.

Marcus Erlandsson, ORSoC



System-on-Module based on an ARM SoC and an ALTERA FPGA

When CPU performance requirement is higher then what a soft processor can offer in an FPGA, how do we solve this without limiting the flexibility and still enable usages of existing IP-cores from OpenCores. One solution that we have now started to developed is an module with an ARM-SoC device tightly connected to an FPGA, a System-on-Module.

Focus for this module will be low cost, connectivity and flexibility.

Module will have a low cost ARM SoC with builtin 4+1 ethernet switch supporting 10/100TX and 100FX on two ports. This ARM device can act as a PCI master. On the PCI bus there will be a USB controller with 5 USB2.0 host ports. Also connected to the PCI bus there will be an ALTERA Cyclone IV with 22KLUT. The FPGA can act as a peripheral controller and/or hardware accelerator for the CPU.

Form factor for this module will be SO-DIMM.

The PCI bus will be present in the board connector thus enabling support for additional PCI connected functions.

This module will be available in industrial temperature range.


Michael Unnebäck, ORSoC



Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Running smoothly

Server information:

  • Replaced a broken router.

Our message to the community:

  • The OpenRISC board with expansion connectors are back in stock again

Marcus Erlandsson, ORSoC





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

Hardware Assisted IEEE 1588 IP Core
Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the high precision Time Synchronization on 1000M/100M/10M Ethernet networks with IEEE 1588(v2). SW will implement the PTP packet transmitting and receiving with existing MAC; The IP Core will implement the adjustable real-time clock and time stamping of PTP packets (L2, UDP/IPv4 and UDP/IPv6) in one-step-mode or two-step-mode.

Minimum set of blocks will be:
RTC: Real Time Clock. Time of Day(ToD) synchronization and Frequency tuning.
TSU: Time Stamping Unit for two-step-mode. Generate Time Stamp for Tx/Rx PTP event packets in two-step-mode.

Additional blocks will be:
TSU: Time Stamping Unit for one-step-mode. Generate Time Stamp for Rx PTP packets and insert Time Stamp for Tx PTP packets in one-step-mode. Ethernet CRC will be regenerated for Tx PTP packets in one-step-mode.
TRU: Trigger Unit. Programmable time triggered output (1PPS) and time stamped input.

The Open Source PTPdv2 will be used for the SW implementation of PTP protocol stack.

Development status: Alpha
License: LGPL
Updates:
Mar 19, 2012: Added TSU parser support for L2, UDP/IPv4 and UDP/IPv6 PTP packets.
Mar 13, 2012: Updated the Description.
Mar 6, 2012: Updated project description.

vSPI
vSPI is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably transfer data at 27.9 mbps on an Atlys FPGA devkit (a Spartan-6 with a 100 MHz system clock).
You can use it to send data between your FPGA/ASIC project and other devices, such as a desktop computer I'm using it to send data between a self-flying RC-helicopter and my PC. If all goes according to plan, I'll be able to see live video from the helicopter's camera on my PC. I'll also be able to inject test data and make sure my logic works with known test vectors.
Development status: Stable
License: Others
Updates:
Mar 26, 2012: Fix minor typo
Mar 26, 2012: Ready to use, updated documentation.
Mar 23, 2012: Set initial state of project

ag_6502 soft core with phase-level accuracy
The main features of ag_6502 implementation:
* It provides not only clock-level compatibility, but phase-level compatibility too. Thus it may be possible to connect simulated 6502 instead of the original one. Source code includes two possibility to simulate two-phase clocking: by the use of external phi1 and phi2 clock generators and by the simulation of the phase shift using higher frequency source (I used standard 50 MHz clock generator to simulate phases phi1 and phi2 in my test project).
* It requires a relatively small amount of FPGA logic, for example in Xilinx Spartan-3E:
- Flop Flops: 93
- LUTs: 978
- Slices: 512
* In the current implementation the following CPU commands are implemented:
- All legitimate commands including ADC/SBC in decimal mode (not all illegal features are fully implemented, such as N, Z flags usage in the decimal mode);
- All KILLs;
- All NOPs including their "addressing modes";
- All LAX illegal commands;
- For all other known illegal commands, only fetch and addressing parts are implemented. No real operations are performed, and timings for these commands may be not accurate.
* All input signals are implemented, including RST, IRQ/NMI interrupts (not tested), RDY line and even SO pin.

Development status: Beta
License: GPL
Updates:
Mar 13, 2012: Added resource consumption image
Mar 13, 2012: Updated description
Mar 13, 2012: Added first release of the project including the test example
Mar 13, 2012: Updated project status

Educational 16-bit MIPS Processor
This project was aimed at providing people a simple, runnable, and easy-to-enhance MIPS CPU main architecture, along with well commented Verilog RTL source code, complete simulation test benches & scripts, and detailed documentation. People can read the source code, make simulations to verify the result, and then make modifications to enhance it. I hope this project can help you learning the MIPS CPU architecture and enjoy constructing your own CPU core. This CPU design is based on Mr. Hu Weiwu’s book ”Computer Achitecture”, Tsinghua University Press, 2011

Technical brief
1. 16-bit data width
2. classic 5-stage static pipeline, 1 branch delay slot, theoretical CPI is 1.0
3. pipeline is able to detect and prevent RAW hazards, no forwarding logic
4. 8 general purpose register (reg 0 is special, according to mips architecture)
5. up to now supports 13 instructions, see ./doc/instruction_set.txt for details
6. Maximum clk Frequency: 82.688MHz on Xilinx 3s1000fg320-5 device (XST).

Development status: Stable
License: LGPL
Updates:
Mar 4, 2012: CPU architecture img add
Mar 4, 2012: file system description added
Mar 4, 2012: description added

MPX 32-bit CPU
‘MPX’ is a 32-bit soft-core processor written in Verilog (and originally in VHDL). It is a pipelined RISC processor which implements the majority of MIPS-I ISA excluding the formally patented unaligned load/store instructions & multiplier / divider (mult, multu, div, divu) instructions. By not including native multiplication & division instructions, the pipeline is simplified and the core is smaller.

GCC was modified to provide the option to disable the MIPS™ mult & div instructions as well as to enable turning off the patented unaligned memory access instructions. Multiplication & division is provided in software by replacement functions in the C library (mulsi3, divsi3, etc), but can optionally be provided by ‘trapping’ on execution of unsupported instructions (hence allowing for a standard release of GCC to be used).

MPX can execute 1 instruction every cycle except for memory access instructions which take 2 cycles (see below). It ‘features’ both a load delay slot & a branch delay slot. When executing from internal single cycle memory, MPX is able to achieve 65.57 DMIPS (Dhrystone 1.1) @ 57Mhz on a Xilinx Spartan 6 FPGA.

MPX is implemented using a 4 stage pipeline;
1. Instruction Fetch
2. Decode & Execute
3. Mem
4. Write-back


Decode & execute are done in the same stage which is not ideal in terms of the amount of logic in a single stage, but it does mean that the decision to branch or not is taken in stage 2 which simplifies the pipeline considerably. As the architecture has a branch delay slot, knowing that you will branch in stage 2 means that you will have also already scheduled a instruction fetch for PC+4 in stage 1, meaning you do not have to flush any part of the pipeline on a branch operation.

MPX is a pipelined Von-Neumann architecture (shared data & instruction bus) which lends itself to connecting to single ported RAM / external memory interfaces. This means that memory access instructions cause a ‘bubble’ instruction to be inserted into the pipeline. Interrupts are also a source of pipeline bubbles. All other data hazards in the pipeline are resolved by forwarding logic. Instruction/Data memory pause (or cache miss) results in the pipelined being stalled.
Development status: Stable
License: LGPL
Updates:
Mar 24, 2012: Added GCC build script
Mar 19, 2012: Added link to MP3 player using MPX core.
Mar 18, 2012: Added GCC binaries for Win32 (modified)
Mar 18, 2012: Added example FPGA project targeting Papilio XC3S250E board.
Mar 11, 2012: Updated project description & uploaded initial code snapshot.

Next 80186 processor
Description
80186 instruction compatible, high performance processor, able to execute up to 40MIPS on a Spartan3AN FPGA. It requires ~1500 slices (25%) on a Spartan3AN. The speed performance is comparable with a 486 in 16bit real mode.

Features
Next186 CPU features:
- All 80186 intstructions are implemented according with the 80186 specifications (excepting ENTER instruction, which uses always 0 as the second parameter - level).
- all 80186 exceptions implemented (divide error - INT0, Trace - INT1, Overflow - INT4, Bounds - INT5, Invalid opcode - INT6, Coprocesor exception - INT7)
- Mascable and non mascable interrupts implemented. If a repeat block instruction is interrupted, the return address is the repeated instruction including all prefixes. This allows fully resume of repeated instruction after interrupt, with no other precautions.
- Designed with 2 buses: 16bit data / 20bit data_address and 48bit instruction / 20bit instruction_address. This allows most instructions to be executed in one clock cycle.
- In order to link the CPU unit on a single memory bus, these sepparate data/instruction buses must be multiplexed by a dedicated bus interface unit (BIU).
- It is able to execute up to 40 MIPS on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU (real mode, 16bit only).
- Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN


Next186 BIU (Bus Interface Unit) features:
- Links the CPU with a 32bit static synchronous RAM (or cache)
- Able to address up to 1MB
- 16byte instruction prefetch queue
- Works at 2 X CPU frequency (80Mhz on Spartan3AN), requiring minimum 2T for an instruction.
- The 32bit data bus and the double CPU clock allows the instruction queue to be almost always full, avoiding the CPU starving. The data un-alignement penalties are required only when data words crosses the 4byte boundaries.

Development status: Stable
License: LGPL
Updates:
Mar 28, 2012: features
Mar 23, 2012: instruction timing
Mar 13, 2012: features
Mar 13, 2012: testbench
Mar 13, 2012: features
Mar 12, 2012: features
Mar 12, 2012: features
Mar 12, 2012: features
Mar 12, 2012: Description
Mar 12, 2012: Description

Bus Transaction Monitor with JTAG
‘A CPU-to-FPGA bus transaction monitor, capturs the CPU write/read address/data to/from memory-mapped registers that resides in the FPGA, and transmitting the captured information to PC through JTAG download cable attached to the FPGA.

The detailed information about this low-level firmware debugger is published by the author on EDN.com as a Design Ideas article: Debug a microcontroller-to-FPGA interface from the FPGA side.

The original source code accompanying this article is set as the code base. And enhancements and additional features will be added.

Release 2.2 Added enhancements:
1. Multiple capture filter selection in the Tk GUI.
2. Read transaction capture.
3. Adjustable pre-trigger capture.
4. Capture content with transaction timing information.

Planned enhancements:
1. Parameterized RTL code for flexible implementation.
2. Comprehensive user guide for implementation and usage.
3. Transaction agent with write/read screening and direct write/read from JTAG.

Development status: Beta
License: LGPL
Updates:
Mar 28, 2012: V2.2 released.
Mar 18, 2012: Bus Transaction Monitor is verified on FPGA in a real product.
Mar 8, 2012: Updated project description.


Johan Rilegård, ORSoC


© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.