Newsletter February 2012
Migen, a Python toolbox for building complex digital hardware
Started late 2011 and still experimental, Migen is a Python-based tool
that aims at automating further the VLSI design process.
Migen makes it possible to apply modern software concepts such as object-oriented programming and metaprogramming to design hardware. This results in more elegant and easily maintained designs and reduces the incidence of human errors.
Built on these principles, it provides or will provide tools to:
-build synchronous designs more productively by automating tasks like resetting registers and abstracting away the event-driven paradigm of HDLs.
- integrate system-on-chips, for example by automatically interconnecting on-chip buses such as Wishbone.
- design hardware accelerators in the dataflow paradigm, with semi-automatic integration in a SoC.
- and more...
For a taste of some Migen code, here is an example of a small SoC design (see for example the Wishbone interconnect): click here
Migen is free software and will become the foundation for the next-generation Milkymist SoC, maintaining the position of the Milkymist coalition - an ad-hoc community comprising about fifteen active developers - as an innovator in open source hardware.
You can find a more complete and technical description of Migen here
To follow and contribute to the development of Migen, feel free to use the public Milkymist development mailing list
Sébastien Bourdeauducq, OpenCores user
Update from OC-Team
This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
This month activities:
- Running smoothly
- No problems.
Our message to the community:
- What functions/features would you like to see on OpenCores?
Marcus Erlandsson, ORSoC
2012 - an exciting year in the FPGA world
After two years with much fuss, Xilinx and Altera will finally begin shipping their new generations of FPGAs manufactured in 28 nm. The first samples were available already last year, this year that volume production will begin and others than a few selected key customers can get their hands on the FPGAs.
28 nm is not only a new process node, Altera and Xilinx will for the first time have the same foundry partner, Taiwanese TSMC. Previously, Xilinx has relied on other companies for manufacturing.
But even if the two rivals use TSMC, they have chosen slightly different versions of the new process. Should we believe the corporate PR machinery the difference is of great importance, but as soon as it will be possible to call the claim we will see if it has any practical significance.
One thing is certain, the new process node gives us so many transistors that you can add a hard-coded, dual-core Arm-processor plus various other hard-coded blocks without too much of a penalty. If these new animals in the FPGA jungle really will be able to grab a slice of the embedded market remains to be seen. At first glance, Zynq and SoC FPGA looks like an interesting alternative to the classic embedded system with a processor, memory, and a FPGA.
And quietly, Micro Blaze will probably continue to triumph. More or less every Xilinx customer uses the soft processor.
The long-standing number three FPGA-vendor, Lattice, has made an interesting come-back. The company seems to have found a niche that the big elephants do not care much about. With its ECP family Lattice can focus on the price and power-sensitive products such as smart surveillance cameras, base stations and other infrastructure for data and telecommunications networks.
Consumer electronics attracts
Last year's acquisition of Silicon Blue also opens a new market - consumer electronics. Price pressures and demands for low power consumption has stopped the FPGAs, only CPLD's has passed the eye of the needle. Silicon Blue is one of the few exceptions, the company's low-power and low cost FPGA implementations have found it's way into smart phones and other battery powered devices. Lattice was able to buy Silicon Blue for only $ 62 million, $ 11 million less than the venture capitalists invested in the company. It seems like the company had trouble monetizing on its FPGA technology. Perhaps it will be easier with the Lattice brand on the circuits?
The deal also gives Lattice access to the nonvolatile memory technology for CMOS that Silicon Blue licensed from KiloPass, a technology that may help Lattice develop the Mach family, who has come to an end with the flash technology used today.
Microsemi, who bought Actel about a year ago, has been quiet after the transaction. One can only speculate on what's happening in the labs, but it is time for the company to show the synergies promised at the time of deal.
Winner Takes it All
2012 should also be the year when we find out if Tabula or Achronix manage to challenge Xilinx and Altera on their main turf - really big FPGAs for telecom and datacom. With Intel's 22 nm process and a big dose of risk capital the case is “make or break”.
And what's happening to Intel's Stellarton, the combination of the Atom processor with an Arria II GX from Altera in the same package? The product was released almost a year ago, but despite repeated requests from Elektroniktidningen, Intel refuses to give any meaningful answers.
By Per Henricsson (firstname.lastname@example.org)
Published by Elektroniktidningen at link
Here you will see interesting new projects that have reached the first stage of development.
Elliptic Curve Group
The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements in the elliptic curve group.
The elliptic curve is super-singular $E:y^2=x^3-x+1$ in affine coordinates defined over a Galois field $GF(3^m)$, $m=97$, whose irreducible polynomial is $x^97+x^12+2$.
The elliptic curve group is the set of solutions $(x,y)$ over $GF(3^m)$ to the equation of $E$, together with an additional point at infinity, denoted $O$. An element in the elliptic curve group is also called “a point”. The elliptic curve group is abelian. The group law is described in the document/specification.
The Elliptic Curve Group core consists of two modules, one computing the addition of two elliptic curve group elements ($P_1+P_2$) and the other computing the addition of many identical elliptic curve group elements ($c⋅P_1$). The first module is called $point_add$. The second module is called $point_scalar_mult$.
The core is written in Verilog 2001, and it is carefully optimized for FPGA. For example, input signals are synchronous and sampled at the rising edge of the clock. Output signals are driven by flip-flops, and not directly connected to input signals by combinational logic. There is no latch, and only one clock domain in entire core.
The $point_add$ module runs at 192 MHz on the Xilinx Virtex-4 XC4VLX200-11FF1513 FPGA board. It computes one addition within 2.7 microseconds if with a 100MHz clock. The $point_add$ module uses 12,099 (6%) LUTs, 6,694 (7%) slices, 6,141 (3%) flip-flops of the XC4VLX200-11FF1513 FPGA board.
The $point_scalar_mult$ module runs at 148 MHz on the Xilinx Virtex-4 XC4VLX200-11FF1513 FPGA board. It computes one addition within 0.552 milliseconds if with a 100MHz clock. The $point_scalar_mult$ module uses 13,780 (7%) LUTs, 7,272 (8%) slices, 7,451 (4%) flip-flops of the XC4VLX200-11FF1513 FPGA board.
- Elliptic Curve Group for hyper-elliptic curve $y^2=x^3-x+1$
- The irreducible polynomial is $x^97+x^12+2$
- Fully synchronous design
- Fully synthesize-able
- ONLY ONE clock domain in entire core
- NO latch
- All output signals are buffered
- Vendor independent code
Development status: Stable
Feb 19, 2012: project description in detail
Feb 16, 2012: add TODO items on web page
Feb 15, 2012: detailed project introduction @ web page
Feb 15, 2012: detailed project introduction
Generic SGMII / 1000X module that can be connected to any transceiver technology.
Development status: Beta
Feb 17, 2012: Testing by simulating with Altera's Transceiver
DDS Signal Generator
Direct Digital Synthesis Signal Generator in VHDL tested and implemented in FPGA (Altera Cyclone 2).
Development status: Stable
Feb 4, 2012: Uploaded the project code as doc format. (Source code in doc)
Feb 4, 2012: Uploaded the project code.
Johan Rilegård, ORSoC