Newsletter January 2012
Positive response for new development board
Since the release date back in November 2011, the interest of this new board has been much higher than we expected. Leading to shortages of products, but we are now back on track and have increased the production speed. For those who missed the last announcement of the we will shortly present the development board again in this article, and also update the OpenCores community with new information.
The development of the OpenRISC processor FPGA development board started because of several reasons:
We needed a good, low-cost FPGA development board that had enough external interfaces so that we could use it as a development platform for the OpenRISC-ASIC project. Allowing OpenRISC community members an affordable, easy hardware platform to test and develop OpenRISC based systems on. More detailed information about the OpenRISC-ASIC project is available here.
We needed an FPGA development platform with Ethernet, USB, SD-card, SDRAM, SPI-flash, on-board JTAG debugging/programming and general purpose IO (GPIO). The problem was that all the cheapest available commercial FPGA-boards didn't support all these interfaces and often came with a to small FPGA, only expensive large FPGA-boards supported all these interfaces. So we decided to develop a FPGA board with focus on the following characteristics:
- Low-cost FPGA board
- Large FPGA allowing a complete OpenRISC SoC system (Altera Cyclone IV FPGA)
- Support for most needed/wanted IO-interfaces
- Small size (40mm x 80mm)
- Easy to connect, using a single USB-cable with multifunction (power, debug, programing,UART)
- Easy-to-use: An VirtualBox-image with all the tools and SoC design pre-installed, really makes it easy to get started. A short video presentation shows how easy it is to be up and running, watch it here.
More detailed information about the OpenRISC development board (Ordb2a-ep4ce22) is available here.
The board is available to purchase at self cost via OpenCores webshop, more details are found here.
Since the launch in November 2011 the interest have been larger then we anticipated, which is great and clearly shows that it was a good decision to develop it. The boards was quickly sold-out and we had to ramp-up the production to meet the increasing demand. Another very pleasant surprise was the interest from commercial companies who are planning to use this board in their commercial products. So for commercial use we can modify the PCB layout so that it match the needed requirements.
We are now thinking of developing an extension board that will be connected to the FPGA-board via the GPIO-connectors. We are interested to get community feedback on what additional interfaces that would be interesting add on this extension board, for example we have had feedback asking for CAN interface. So what interfaces would you like to be added?
Update from OC-Team
This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
This month activities:
- A minor bug fixes, still working on some of them
- No problems.
Our message to the community:
- The new OpenRISC FPGA development board was quickly sold-out after the launch, but is now available again.
- Please help us improving OpenCores, send us bug-reports and ideas of new features/functions.
Marcus Erlandsson, ORSoC
Apple, the largest semiconductor buyer
In just a few years Apple's success with iPhones, iPads and flash-based netbooks have propelled
the company to the top of the list of the largest buyers of semiconductor devices, according to the
analyst firm Gartner. Last year Apple dethroned longstanding leader HP.
The ten largest buyers of semiconductors accounted for 35 percent of the market last year. That corresponds to semiconductor chips with a value of $ 105.6 billion in a market that was worth a total of 302 billion dollars. The ten largest buyers increased its share by 1.8 percent compared to 2010.
If you look at the list of the semiconductor companies ten largest customers, it's like they played musical chairs last year. Apple and HP switched places, Nokia slipped one place to fifth while Dell advanced one place to fourth, despite the fact that both companies turnover decrease.
A company that grew substantially, although not as strong as Apple was Lenovo, which increased by 23.7 percent.
|2010||2011||Company||2011||2010||Growth (%)||Share (%)|
Sales in billions of dollars.
* Nokia's and Sony's sales excluding Sony Ericsson and Nokia Siemens Networks
Published by Elektroniktidningen at link
Here you will see interesting new projects that have reached the first stage of development.
PS/2 Host Controller
This core aims at implementing host side of IBM PS/2 keyboard and mouse communication protocol.
Development status: Beta
Dec 19, 2011: Add information about how to run testbench.
Dec 16, 2011: Adding a brief description of the project.
Dec 16, 2011: Moving core to "Communication controllers" category. Previously it was wrongly assigned to "Arithmetic cores".
DSP WishBone Compatible Cores
This project contains three DSP Wishbone compatible cores.
1. IIR (Second Order Sections) core.
2. FIR (Transpose Structure) core.
3. FFT (R2^2 SDF Structure) core. Based on Master Thesis "Development and Verification of Parameterized Digital Signal Processing Macros for Microelectronic Systems" by Adam Robert Miller.
All cores are fully parametrizable and Wishbone compatible. For FFT core, sizes ranging from 2 to 1024 are allowed.
A HAL (Hardware Abstraction Layer) over minsoc project, is included.
Development status: Mature
Tate Bilinear Pairing
This hardware IP core can do Tate pairing.
To date the Tate pairing is the most efficiently computable bilinear pairing on elliptic curves. Over supersingular elliptic curves it achieves its maximum security in characteristic three.
Development status: Mature
Jan 17, 2012: update the introduction of Tate bilinear pairing project, upload some RTL code
Viterbi Decoder (AXI4-Stream compliant)
A fully configurable VHDL Viterbi decoder compliant with the AXI4-Stream interface. Most standards using convolutional codes like Wifi or GSM are easy to implement by configuring some generic parameters. The decoder supports a high throughput even on low-cost devices.
•Design-time configuration of encoder polynomials (different number of states and different code rates).
•Support for recursive and non-recursive convolutional codes.
•Windowing technique for reduced latency and memory requirements (with acquisition).
•Design-time configuration of quantization, maximum window size, RAM usage (distributed RAM vs. Block RAM).
•Run-time configuration of block length.
•Run-time configuration of window length and acquisition length.
•Block-to-block on-the-fly configuration.
•Comprehensive documentation available.
Development status: Stable
Jan 17, 2012: Communication Performance of a Viterbi Decoder
Jan 17, 2012: Viterbi core now online and available
16/32 bit SDRAM Controller
• 16/32 Configurable SDRAM data width
• Programmable column address
• Support for industry-standard SDRAM devices and modules
• Supports all standard SDRAM functions
• Fully Synchronous; All signals registered on positive edge of system clock
• One chip-select signals
• Support SDRAM with four bank
• Programmable CAS latency
• Data mask signals for partial write operations
• Bank management architecture, which minimizes latency
• Automatic controlled refresh
• Static synchronous design
• Fully synthesizable
Development status: Stable
Jan 22, 2012: SDRAM Controller with 16/32 Bit Basic design is completed with automated testbench
Jan 18, 2012: 16/32 Bit SDRAM Controller verilog RTL with Automated Test bench are uploaded into SVN under sdr_ctl project. Interested user are welcome to validate the IP.
Johan Rilegård, ORSoC