Newsletter November 2011
The new OpenRISC FPGA development board - the easy way
The newly developed OpenRISC development board available from the OpenCores webshop serves a number of purposes. For anyone interested in trying out the OpenRISC this board provides an easy path. The board is shipped with with a preinstalled bootloader that can boot Linux, either from a FLASH SD card or over Ethernet via TFTP. Others more interesting in developing the SoC the FPGA offers a large number of resources for many types of functionalities.
An accompanying Virtual Box image is available with all necessary tools for software development. This image also has preinstalled applications to reconfigure the FPGA and program on board FLASH resources.
When used as a development board you usually connect to a PC over USB. In this case the USB has the following functions:
1. Supply the board with 5V
2. JTAG for FPGA configuration
3. SPI for FLASH configuration (used for FPGA configuration and boot loader and optionally Linux)
4. UART used as console in Linux
5. UART for application
The board has two optional expansion connectors on the bottom side. Intended use is to have this board mounted on a carrier board in situations where the applications requires resources not found on the board itself. This would typically be connectors and accompanying functions for field buses, audio or video.
The board has the following functions:
2. SDRAM memory
3. FLASH memory / SD micro connector
4. USB host/slave
6. Expansion options
The FPGA was chosen based on the following: - Enough resources in terms of logic and memory to build an OpenRISC based system supporting all peripherals on board.
- A package with low area
- A low cost FPGA that could be used in products with moderate volume
The choice was ALTERA Cyclone IV. With the Quartus tools supporting ALTERA devices a solid flow for implementation is present. Also the TimeQuest timing analyzer gives the user excellent support for timing constraints. There exist also a path towards HardCopy for price sensitive product segments.
As SDRAM standard SDR types are used. That enable us to use an open source memory controller. SDR SDRAM is also a very low cost solution. The board supports different clocking scemes for the SDRAM. The default sources the SDRAM clock from the FPGA.
SPI FLASH is used for storage of both FPGA configuration and instruction memory for the OpenRISC. The board also supports SD card. One usage for this would be to store a Linux image.
The board has support for both USB host and peripheral modes. An external level shifter is used to produce USB standard signaling levels. Configuration signals are used to enable either slave or peripheral mode. Necessary pull-up and pull-down resistor for different modes of operation are available on board. The USB connector for this is micro AB. With appropriate cabling other types are supported, such as type A.
The Ethernet solution is based on an Ethernet PHY from Micrel. This device uses a low pin count RMII interface limiting the IO count for this interface. This interface also present both RX and TX signal in one common clock domain. This device is in a very small QFN package occupying only 4x4 mm PCB space.
The board is supplied with 5V, normally from the USB configuration connector. Optionally supply can come from one of the expansion headers. Local DC/DC converters are used for all supplies on board. Very compact converters were chosen to save board space. An other benefit with the chosen converters are that they have programmable output levels hereby enableing us to use the same type of converter for different supplies without the need for external feedback resistors. The inductor is included in a 5x4 mm QFN package.
Configuration, UARTs and debug communications is handled with a quad USB to serial controller from FTDI. With this setup it is possible to use freely available open source tools for configuration of the FPGA. Virtual box image has UrJTAG installed.
Variants on this board can be produced for special purposes. Also different types of IO boards can be made available.
The intention is that this board will provide an easy path for software developers and at the same time offer a compact and price/performance optimized platform for new exiting products.
Read more about the board here.
Micahel Unneback, ORSoC
OpenRISC Ubuntu VirtualBox image - get started quickly
The purpose with this Ubuntu-VirtualBox-image is to enable users to quickly and easy get started with the OpenRISC processor, without having to follow several installation guidelines, causing installation errors for many users.
In order to eliminate these installation issues, that are much easier to solve/handle later on when the user have become more familiar with the OpenRISC platform, we have created an Ubuntu VirtualBox image that contains all the necessary tools pre-installed. The VirtualBox-image includes the following:
- Ubuntu 11.10 Linux distribution installation
- OpenRISC toolchain install for both baremetal and Linux applications - GCC,GDB, Libs etc.
- OR1KSIM - OpenRISC architectural simulator
- OR_DEBUG_PROXY - enabling hardware debugging, FPGA programming and SPI-flash programming - ICARUS Verilog simulator
- ORPSoCv2 - OpenRISC Reference Platform SoC with support for the NEW OpenRISC development board (ordb2a-ep4ce22)
- Hardware tutorial for the ordb2a-ep4ce22 board
- OpenRISC Linux3.1 port with support for the ordb2a-ep4ce22 board
- Get-started tutorial (HW & SW simulations, FPGA programming, SPI programming etc)
- SPI flash programming tool for ordb2a-ep4ce22 board
Here is a VirtualBox installation video that also shows quickly how easy the new OpenRISC board is up have running: video clip
The new OpenRISC-FPGA-development board (ordb2a-ep4ce22 board) is supported in this VirtualBox-image. Read more about the NEW OpenRISC board here
Download the NEW OpenRISC-Ubuntu-VirtualBox-image here
Our mission/goal with this VirtualBox-image and with the OpenRISC development board is to spread the OpenRISC processor awareness and hopefully get more contributers into the project.
So join the OpenRISC-project!
Marcus Erlandsson, ORSoC
Altera teaches FPGAs to talk OpenCL
Altera is developing a tool that allows you to run OpenCL programming language on an FPGA. OpenCL is a common programming language for graphics processors and CPUs - and now even FPGAs.
Altera has a prototype tool that takes OpenCL code as input and generates code for its own FPGAs, "with good performance," according to Altera.
Climate and financial modeling, radar, medicine, and supercomputer calculations in general - there are some areas where Alteras new tool now being tested.
Quick calculations were carried out in the past on CPUs. Today, try to also involve other types of processors in the work. Graphics core - which is massively parallel - was an early candidate.
The open standard, OpenCL has been one of the tools for achieving this. Now offering Altera into the even more massively parallel FPGA cores in the game using OpenCL.
Altera also want to influence the next generation of OpenCL to customize it more for the type of memory interface FPGAs using.
Today's supercomputers are already hybrid solutions that not only use CPUs, but GPUs - and FPGAs - for number crushing. With a common programming language makes it easier to stitch together heterogeneous systems of that kind.
The technology is interesting beyond the field of supercomputing. It was Apple that brought out the first proposal for OpenCL. In particular, it has been interested in relieving classic CPU work to the GPU.
Alteras tool support systems that mix ARM and x86 CPUs with programmable logic. Support for additional one CPU architecture to be announced in 2012.
The tool is under development and Altera has not launched any products yet.
Altera has been a member of the Working Group on OpenCL since January last year.
Published by Elektroniktidningen at link
Update from OC-Team
This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
This month activities:
- A bug with the mailman-system, now fixed.
- A harddisk failure on one of the servers.
Our message to the community:
- Checkout the new OpenRISC FPGA development board and Ubuntu-VirtualBox-image, it has never been easier to get started with the OpenRISC processor platform.
- Please help us improving OpenCores, send us bug-reports and ideas of new features/functions.
Marcus Erlandsson, ORSoC
Here you will see interesting new projects that have reached the first stage of development.
OP2P (OpenPeerToPeer Interface)
Open Peer to Peer Interface, Wishbone to Aurora Bridge (OP2P). This interface logic has been designed to provide a very high performance multi-lane multi-gigabit fully non-transparent (independent address spaces) peer-to-peer (no master/slave or root-complex/endpoint relationships) communiction link where the rest of the communication stack is implemented in hardware. It can be used for both cable or backplnane links. The aim of the project is to provide a network-like, high-bandwidth, flexible, serial-I/O-based replacement of originally PCI-based multi-processor and storage systems.
The destination of a transaction is specified with a 16-bit ID which is made of a 10-bit chassys ID and a 6-bit slot-ID. For point to point cable links we can use ID=0 which means the packet is intended for the device receiving it (the link partner). The OP2P protocol supports multi-hop mesh topologies where not every card has direct conenction to every other (like in a full-mesh), and the device receiving a packet with a non-matching destination ID will forward the packet on another port to reach the inteded recipient. This is called distributed switching, no switch cards are needed in the system/network. The system or network can be backplane-based or cable-based, or a mixture of them. There are similarities with PCI-express in the way of handlindling the packets, but without the limitation of speed, number of non-transparent ports on a device and the master-slave relationships. There are also similarities with Ethernet, without the excessive software overhead and the limitations of the link-width and speed unflexibility.
This IP core is only one port. It implements a higher (transaction) layer of the communication stack, while the lower (physical) layer is implemented inside the Xilinx Aurora interface IP (using various types of the Xilinx multi-gigabit serial transceivers) generated in the Xilinx CoreGenerator program. The OP2P interface was developed to provide a low latency, low software-overhead board-to-board communication interface. It is basically a “Buffer-Copy” interface; it copies data from a DRAM memory buffer on one board to a memory buffer on another board, initiated by a command which specifies the address locations within both the source and the target buffers. The buffers should be memory mapped within the system address spaces of the boards independently (PCI/PCIe devices). It is based on PCI-express, with certain modifications: all ports are non-transparent and peer-to-peer supports packet forwarding in indirect mesh connections without the on-board system processor’s (usually X86 high performance processor like Intel Core-x, Xeon…) intervention. This interface cannot be used to replace a master-peripheral type PCI system, since it requires more intelligence in a peripheral card, and it is not compatible with the PCI Plug&Play BIOS/software, also all ports are non-transparent. The host (x86) processor does not read/write data directly from/to the OP2P port, but instead it provides a command (fill up 5 FIFOs with transaction parameters) to allow the OP2P port logic to take the data from/to the local DRAM buffer. A complete bridge/switch (FPGA chip logic) would consist of multiple OP2P ports with a local DRAM buffer, and the host (X86 processor) will have to read/write that DRAM buffer directly instead of reading/writing the ports.
Development status: Beta
Nov 14, 2011: updated description about series-7 FPGA compatibility Nov 10, 2011: project created
copyBlaze is a from-scratch synthesizable & behavioral VHDL clone of Ken Chapman's popular 8bit PicoBlaze embedded microcontroller. It support wishbone interface.
Assembler and C Compiler are used in the developpement.
Development status: Mature
Nov 28, 2011: use the PicoBlaze C Compiler (PBCC)
Nov 27, 2011: add wishbone block
Nov 26, 2011: minor
Nov 25, 2011: Add STATUS block
Nov 22, 2011: Synthesis result
Nov 21, 2011: ROM Dimension
Nov 20, 2011: update target
Nov 20, 2011: change Licence type
Nov 19, 2011: Evolution
Nov 19, 2011: Features
Nov 19, 2011: features + code + test + todo
Nov 19, 2011: features
Nov 18, 2011: Update the generale information of the project
Johan Rilegård, ORSoC