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NEWSLETTER JUNE 2011

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New OpenRISC project page

In order to make the OpenRISC project even more successful and enable more users to contribute, we have added the following features/functions to the OpenRISC project page:
- Wiki page
- Mailman (mailing-list system)
- GIT (revision control system)
- Bugzilla (bug tracker system)

Read more...


OpenRISC ASIC donation status

OpenCores has now added a new web-forum dedicated for discussion related to this topic...

Read more...


Design for portability - interconnection

The second article covering various aspects of importance for making a design modular and portable. This time we cover the topic of interconnection standard - Whishbone.

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

Read more...

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Newsletter June 2011


NEW OPENRISC PAGE

In order to make the OpenRISC project even more successful and enable more users to contribute, we have added the following features/functions to the OpenRISC project page:

- Wiki page
This enable the OpenRISC community to easily add/modify the information presented at the project page. We encourage the community to help to keep the information up to date and to add more how-to guides, installations guides, FPGA development board support etc.

- Mailman (mailing-list system)
We get allot of feedback from the community about wanted features and functions, and it seems to be two strong groups within the community, one that wants web-forum and one that wants mailing-lists. We have now added mailing-lists in order to please all parties. We are now implementing functions enabling us to integrate these two together, so that posts do not need to be sent to both systems. All OpenCores users that are subscribing to the OpenRISC-web-forum are also automatically subscribing to the OpenRISC-mailinglist, and can also email posts directly using the email address that was used during the OpenCores registration.

- GIT (revision control system)
This feature has also requested by multiple users, mainly from users developing software (e.g Linux kernel development). Allowing the maintainers to select the tool that suits their specific need best.

- Bugzilla (bug tracker system)
Based on the size and increasing activity of the OpenRISC processor, we needed to move to a more advanced bug tracker system. Bugzilla provides the necessary features to keep track of potential bugs and requests. This features will is still under testing and will hopefully be released within 1-2 weeks. They current plan is to move for all open-bugs to Bugzilla and then close the old bugtracker for new enties. The old-bugtracker will still be availabe as read-only for history.

Marcus Erlandsson, ORSoC





OpenRISC ASIC donation status and discussion

We have been focusing on spreading the word about this project to other communities and news-magazines. Our initial estimation is that we need more fundings in order to make sure that we can get sufficient system performance and low unit-price. We have also sent an email to the current donors asking them how they want to "communicate" and the majority of users wanted a web-forum. So we have now started a new web-forum targeted for the OpenRISC-ASIC related discussions. Check it out here.

We are today 370 donors with a OpenRISC-ASIC fund of $16560.

So to kick-off the discussions, please get involved on the web-forum and for example discuss what we together need to do to get more donations.

Thanks, OC-team





Design for portability - interconnection

At OpenCores we have agreed upon a interconnection standard. Having a well known and widely used interconnect method makes it easier to adopt IP cores.

The WISHBONE System-on-Chip (SoC) Interconnect Architecture for Portable IP Cores is a portable interface for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating system-on-a-chip integration problems. This is accomplished by creating a common, logical interface between IP cores. This improves the portability and reliability of the system, and results in faster time-to-market for the end user. WISHBONE itself is not an IP core...it is a specification for creating IP cores.

The WISHBONE standard is not copyrighted, and is in the public domain. It may be freely copied and distributed by any means. Furthermore, it may be used for the design and production of integrated circuit components without royalties or other financial obligations.

The WISHBONE design specification can be used for both point to point interconnect and for one to many or many to many. Addressing is done in a memory mapped fashion. Many different type of bus cycles are supported including burst transfers.

The latest release, B4, adds some functionality not found in earlier releases. A pipelined traffic mode is introduced. This is especially useful for peripherals with high latency and high throughput, such as SDRAM. In pipelined mode a new transaction can be issued at each cycle without the need to await completion of earlier transactions.

For in depth details regarding WISHBONE the specification is freely available at http://opencores.org/downloads/wbspec_b4.pdf

Michael Unnebäck, ORSoC





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Added a new web-forum (OpenRISC-ASIC-funding).
  • Redesigned the OpenRISC processor project page. Added Wiki, Mailman, GIT and Bugzilla.

Server information:

  • Invested in a new server.
  • The servers has been running without any issues.

Our message to the community:

  • Please join the OpenRISC-ASIC donation project
  • Marcus Erlandsson, ORSoC





    New IP-cores

    Here you will see interesting new projects that have reached the first stage of development.

    Population Counter Generator
    C code for generating a stand-alone population counter with user-defined size (number of input bits) and latency (number of clock cycles) in VHDL.
    Development status: Stable
    License: LGPL
    Updates:
    Jun 27, 2011: description

    all-pole IIR filters
    The circuits found here implement digital leapfrog filters. All filters ar of lowpass type. They are optimised in terms of area.

    This kind of filter structure is the digital counterpart of an analog lumped-elements ladder filter. It simulates the functioning of an all-pole lowpass filter under the assumption of a large oversampling. The circuit implements the integral relations between voltages and currents of the capacitors and the inductances with the help of accumulators. This corresponds to simplify the Z-transform to z = 1 + sT.

    The relative values of the filter coefficients specify the transfer function shape (Butterworth, Chebyshev, ...). The amplitude of the coefficients specify the cutoff frequency. In the circuits provided here, this amplitude is set by a shift value given as a generic.

    The filter provided are
    - a 3rd order Butterworth with no multiplier (coefficients are only shifts)
    - a 6th and an 8th order Bessel with coefficients optimised to 2 shifts and an addition
    - a generic filter wher the coefficient multiplications are executed iteratively
    Development status: Beta
    License: LGPL
    Updates:
    Jun 15, 2011: first tested blocks. General filter to follow
    Jun 11, 2011: testing


    Johan Rilegård, ORSoC


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