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NEWSLETTER MAY 2011

www.orsoc.se

Additional call for donars - create the worlds first open-source OpenRISC processor ASIC

Help us create a "super-low-cost" SoC ASIC component based on the OpenRISC processor, offered back to the community at self-cost using a "flat-rate" price model ...

Read more...


Design for portability

This is the first article covering various aspects of importance for making a design modular and portable.....

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

Read more...


Almost as good as an asic

With Easicopy, eASIC takes a further step towards the asic side by offering customers to convert their designs done in Nextreme to an ASIC.

Read more...

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Newsletter May 2011


Additional call for donars - create the worlds first open-source OpenRISC processor ASIC

Help us create a "super-low-cost" SoC ASIC component based on the OpenRISC processor, offered back to the community at self-cost using a "flat-rate" price model . THIS IS UNIQUE AND HAS NEVER BEEN DONE BEFORE IN HISTORY, SO PLEASE JOIN US.

So come on OpenCores users, so far 348 users have donated fundings to this "ground-breaking" project. If we ALL pitch in, we can really enable this project to afford the most optimum ASIC technology, enabling us all access to a super-low-cost OpenRISC processor ASIC component that can be used in hobby- and commercial products.

We are today ~120.000 OpenCores users, so we REALLY encourage more users to donate and to give us a chance to prove that this project will be a success and that it will be "the new way" of developing cost-efficient open-source ASIC components. Why should we all create our own ASIC when we can share it, and especially share the costs and gain from the "flat-rate" price model.

Below are some facts about the project and important FAQ's:

  • Create an open-source ASIC component based on the OpenRISC processor and peripheral functions.
  • Enable the community to buy it at self-cost, using a "flat-rate" price model, meaning that that unit-price is the same regardless volume. The annual price negotiation towards the ASIC-manufacturer will be based on the accumulated volumes of all OC-users, so we will all gain when volumes increases and if more users starts to use it frequently.
  • The SoC-design proposal that are presented on the donation web page (or1k-asic.pdf) is only a preliminary proposal, since it depends heavily on what kind of ASIC-technology we can afford. We plan to invite all donars to provide feedback on wanted functionality/configuration.
  • Paypal alternative, it's also possible to donate money via a traditional bank wire-transfer. Send us an email and we can provide you with the information (oc-team@opencores.org).

We humbly ask the OpenCores community to help us make this project come true!

Thanks, OC-team





Design for portability - Coding tips of the month

This is the first article covering various aspects of importance for making design modular and portable. The intention is to publish the content in a document.

Design for portability

At OpenCores we have portable open source IP in most cases written in a hardware description language such as Verilog or VHDL. In this case the use of a defined language is important since that ensures that the design can be simulated and implemented using standard simulation and synthesis tools available from multiple vendors and in some cases as open source software. This is especially true for simulation where there exist some alternatives.

  • VHDL open source simulator
    • GHDL
  • Verilog open source simulator
    • Icarus
    • Verilator
  • Waveform viewer
    • GTK Wave

Other aspects that are important to ease portability

  • design readability
  • usage of common interconnect standards
  • target technology independence
  • availability of test cases
  • availability of timing constraints

Design readability

To ease readabilty of design we have at opencores agreed on coding guidelines. This guideline contains naming conventions of signals and modules/entiies in a design.

The following list is an excerpt from "OpenCores Coding Guidelines"

  • *_i Cores input ports
  • *_o Cores output ports
  • *_io Cores bidirectional ports
  • *_clk_i Cores clock input
  • *_clk_o Cores clock output
  • *_rst_i Cores reset input
  • *_rst_o Cores reset output
  • wb?_*_i Cores wishbone input port where ? represent optional letter for defining slave (s) or master (m) signals
  • wb?_*_o Cores wishbone output port where ? represent optional letter for defining slave (s) or master (m) signals
  • *_pad_i Core signals to be connected to pads
  • *_pad_o Core signals to be connected to pads
  • *_padoe_o Core signals connected to pad output enable
  • *_clk_pad_i Clock input connected to pad
  • *_clk_pad_o Clock output connected to pad
  • *_rst_pad_i Reset input connected to pad
  • *_rst_pad_o Reset output connected to pad

Of importance is also to follow the recommended directory structure. This structire defines where to put RTL source code, test benches, simulations scripts, timing constraints etcetera. A common structure make it much easier for a user to adopt an existing design. Information regrding directory structure is also found in the OpenCores Coding Guideline.

Michael Unnebäck, ORSoC





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Fixed Forum bug, creating duplication of posts.

Server information:

  • Running without any issues

Our message to the community:

  • Please make a donation to the OpenRISC-ASIC project
  • We will shortly improve the FAQ-pages, in order to make it more clear about the reasons why we add/change different functionalities. It's important to understand these details since we are trying hard to improve OpenCores (web-page, statistics, quality of IP-cores etc).
  • Please help us improving the project statistics by answering on the "feedback email" sent automatically to all users after downloading a project (sent two weeks after the download).

Marcus Erlandsson, ORSoC





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

SPI Master/Slave Interface
SPI master and slave interfaces in VHDL, with fully pipelined RTL architecture and separate clock domains for the SPI bus clock and parallel I/O interface. Supports via VHDL Generics all SPI modes (CPOL / CPHA), configurable number of bits (N) and PREFETCH lookahead data request for pipelined sync. This core is a fully static design and is very simple to use. The parallel read/write ports are used like synchronous RAM memory ports. For a 32 bit word size, the master module takes 25 slices (76 FFs) on a Spartan-6 device, and the slave module takes 46 slices (81 FFs). This design works at 25MHz SPI bus clock domain and 125MHz parallel clock domain on a Spartan-6 device speed grade -2.
Development status: Beta
License: LGPL
Updates:
May 30, 2011: v0.95.0050: uploaded project files.
May 22, 2011: Updated description and design frequency.
May 18, 2011: Updated description
May 18, 2011: Added features block
May 18, 2011: Updated project description.
May 18, 2011: Updated project description.
May 18, 2011: Change project category to "communications controller". Upload source files.

Present - a lightweight block cipher
Present is a lightweight block cipher dedicated to implement in Hardware. It was developed by Knudsen team. This cipher operates on the 64 bit text with use of 80 bit key. It contains S/P blocks and xor operations for encryption and key update through 32 rounds. In this project I plan to create: - Present module dedicated to 32 bit Hardware (32 bit I/O and working under state machine)
Development status: Beta
License: LGPL
Updates:
May 9, 2011: Added description in the project page

Three compact implementations of AES encryption
Three iterative implementations of AES encryption that can be used to implement an AES-CCM core.

Architecture 1
Iterative not-folded architecture with 16 S-Boxes implemented in 8 dual-port rams in the FPGA BlockRAM. The MixColum operation is implemented by bitwise operations.
Synthesis: 35 Slice Registers, 801 Slice LUTs @ 183.036 MHz

Architecture 2
Iterative not-folded architecture with 16 S-Boxes implemented in 8 dual-port rams in the FPGA BlockRAM. The MixColum multiplications in Galois Field GF (2^8) are implemented in 32 look-up tables.
Synthesis: 146 Slice Registers, 483 Slice LUTs @ 237.620 MHz

Architecture 3
Iterative folded architecture with 4 S-Boxes implemented in two dual-port ram in the FPGA BlockRAM. The MixColum operation is implemented by bitwise operations.
Synthesis: 439 Slice Registers, 335 Slice LUTs @ 233.503 MHz
Development status: Alpha
License: LGPL
Updates:
May 11, 2011: Editing project info.

Pepelatz MISC
Pepelatz MISC is a very small 16-bite processor written on Verilog. It can be used for learning Verilog HDL and computer low-level architecture.
Development status: Planning
License: LGPL
Updates:
May 25, 2011: Editing main page.
May 7, 2011: Creating pages...
May 6, 2011: I have added a short descriptor. Sorry for my English...

Async-SDM-NoC
Asynchronous networks-on-chip (NoCs) provide low power, low latency and sometimes low area on-chip communication fabric for MPSoCs or CMPs. Asynchronous NoCs are naturally tolerant to all variations, which is a serious design issue in synchronous circuits coming along with the technology scaling.
The asynchronous spatial division multiplexing (SDM) router projects provide asynchronous router designs using the SDM flow control method instead of VC. It is found SDM can provide the same network throughput with less area and power overhead than VC.
All routers use 4-phase 1-of-4 pipelines (relaxed-QDI, or self-time in a strict opinion, no delay matched lines).
Development status: Planning
License: LGPL
Updates:
May 21, 2011: Warning notice May 10, 2011: change the ASYNC-SDM-NoC project to SoC group

CCSDS RX_TX_SoC
Software Defined Radio RX/TX.
Consultative Committee for Space Data System (CCSDS) specifications compliant.
This is part of a larger project to implement Nasa Space Telecommunication Radio Systems (STRS) architecture for flexibility, reconfigurability and evolutivity.

Protocol description
- Open System Interconnection (OSI) philosophy : reduced to 5 layers as CCSDS Space Communications Protocols Reference Model

Emitter (TX) description:
- Application Layer: Lossless Data Compression or Image Data Compression + CCSDS File Delivery Protocol (CFDP) or Space Communications Protocol Specifications - File Protocol (SCPS-FP) / FTP
- Transport Layer: CCSDS File Delivery Protocol (CFDP) or Space Communications Protocol Specifications - File Protocol (SCPS-TP) / FTP or User Data Protocol (UDP) + Space Communications Protocol Specifications - Security Protocol (SCSP-SP) or IPSEC
- Network Layer: Space Packet Protocol or Space Communications Protocol Specifications - Network Protocol (SCPS-NP) or IP-v4 or IP-v6
- Data Link Layer - Protocol Sublayer: Telemetry (TM) Space Data Link Protocol or Telecommand (TC) Space Data Link Protocol or Advanced Orbiting Systems (AOS) Space Data Link Protocol or Proximity-1
- Data Link Layer - Synchronization and Channel Coding Sublayer: Telemetry (TM) Synchronisation and Channel Coding or Telecommand (TC) Synchronisation and Channel Coding or Proximity-1
- Physical Layer: RF and Modulation Systems or Proximity-1

Receiver (RX) description:
- Physical Layer: Demodulation - implementation of "Autonomous Software-Defined Radio Receivers for Deep Space Applications" recommandations from Jon Hamkins and Marvin K. Simon
Development status: Alpha
License: LGPL
Updates:
No news

Graphics Accelerator
This project is a group of hardware units that perform graphics algorithms.
For testing purposes, beside the Units that perform these algorithms, there is a Frame Buffer that holds the image drawn and a Video Controller that outputs the image to a screen. In addition to the user interface which consists of switches and push buttons that selects the color, position, function performed, .. etc.
Development status: Beta
License: LGPL
Updates:
May 17, 2011: Added the Abstract of the project


Johan Rilegård, ORSoC



Almost as good as an asic

Easic is an odd alternaive in the FPGA and ASIC world with its Structured ASIC Nextreme. With Easicopy the company takes a further step towards the asic side by offering customers to convert their designs done in Nextreme to an ASIC.

The idea is that customers will kick off with Nextreme but when they see the product hit the market and volumes begin to rise they can start the conversion process. The arguments are similar to those from Altera, when talking about Altera Hardcopy: cheaper, lower power consumption and better performance.

- Hardcopy is good when you have volumes of a around tens of thousands of circuits per year. In this volumes Easic promote Nextreme as an option. Our cross over point for Easicopy is around 300 000-900 000 circuits a year, "said Narinder Lall from Easic.

One of the reason for the large difference is that a structured asic is always cheaper to manufacture than an FPGA, because it does not need as much silicon. Another difference is that Hardcopy is a smaller step to take than Easicopy because in Hardcopy you only program the vias between four layers while Easicopy basically is the same thing as making a complete ASIC design.

- There is less risk with Easicopy compared to doing a full asic and it also allows you to sell products based on Nextreme while working on the ASIC.

One early customer is the hard drive manufacturer Seagate that has developed a hybrid disc with both flash memory and magnetic memory. The first disks contained a Nextreme device but as the product sold well, it has been converted into an ASIC chip using Easicopy.

The conversion is done by Easic and costs almost as much as when you make an ASIC from scratch. The duration is somewhat shorter because much of the netlist and timing conditions from the design of Nextreme can be reused.

Then it takes just as long as with any other ASIC to produce it in the foundry.

Besides that you lower the cost, decreases power consumption and can, for good and for bad, also have a circuit that in some cases is faster than the original.

About Nextreme
Nextreme is a structured ASICs where only connections (vias) between two of the methal layers needs to be programmed. Initially Nextreme was produced in a 90 nm process, but in 2008 the company took a step to 45 nm in conjunction with the launch of the Nextreme-2. The family is available with up to 20 million gates, which in FPGA terms equals to roughly 1.9 million four-way lookup tables. With a better clock speed of up to 700 MHz, lower power and lower price it is already a compelling alternative to FPGAs for big companies.

Published by Elektroniktidningen at http://www.etn.se/53837




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