OpenCores

OpenCores.org

NEWSLETTER APRIL 2011

www.orsoc.se

Help us "revolutionize" the hardware industry - Creating the worlds first open-source OpenRISC ASIC

Help OpenCores create a "super-low-cost" SoC ASIC component based on the OpenRISC processor. This ASIC will then be offered for sale to the community to use freely in any products, especially for the donors. Your donation is very important allowing us to implement the design into a cost-efficient ASIC technology.

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
- Just smaller bug fixes
- Replaced a broken harddisk

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

Read more...


OpenCores is the world's largest site/community focusing on open source hardware IP core development.

OpenCores Newsletter is published once a month - it gives you the latest news and updates at the site/community.

Do you wish to unsubscribe from this newsletter - uncheck the subscription button in your account settings at OpenCores.

(c) Copyright Opencores.org, equivalent to ORSoC AB. All rights reserved. OpenCores®, registered trademark.



Newsletter April 2011


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Just smaller bug fixes

Server information:

  • Replaced a broken harddisk

Our message to the community:

  • Please help us improving the project statistics by answering on the "feedback email" sent automatically to all users after downloading a project (sent two weeks after the download)

Marcus Erlandsson, ORSoC





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

High Latency Bursting WISHBONE Wrapper for Xilinx MIG
Two WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback Incrementing Burst Cycle. The second is a non-compliant but streamlined interface developed as a proposal for inclusion as a new Burst Cycle Type geared towards interfacing with high latency devices.
Development status: Planning
License: LGPL
Updates:
Apr 7, 2011: Updated description

Turbo/Toy System Verilog Compiler
This is a project help hardware design.
Development status: Planning
License: Others
Updates:
Apr 12, 2011: Tools detail info

Generic APB register file
Generic APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet.
Development status: Mature
License: LGPL
Updates:
Apr 19, 2011: description
Mar 30, 2011: Initial files upload
Mar 30, 2011: Initial files upload

PCIe_mini (PCI-Express to Wishbone Bridge for Xilinx FPGAs)
Very often we want to make a peripheral card or a peripheral block on an x86 motherboard using an FPGA, but not necesserily want to spend a lot of time on developing common blocks (like a PCI-express interface), we want to focus on our own custom logic design instead and use completely implemented IP cores for the common blocks. The "mini" in the name doesn't refer to a minicard formfactor, but it just signifies that the core is small and is implemented as a single VHDL file. This is a simple implementation of a PCI-Express target to Wishbone master bridge.

The Xilinx Series-5/6 FPGAs have a built-in PCI-Express Endpoint Block, however it does not contain the packet encoding/decoding logic. This IP core (pcie_mini) implements the missing parts of the Xilinx core and also adds a Wishbone back-end interface. Strangely the Xilinx PCIE-EP handles packet encoding/decoding for configuration accesses, but not for memory accesses. This core interfaces the Xilinx PCIE-EP with its Transaction (TRN) interface. The Xilinx Series-7 FPGAs have a more complete PCIE-EP, but they also support using the TRN interface, so this core should work with them as well. The user has to use the Xilinx Coregenerator to generate a PCIE-EP wrapper (xilinx source files) for the chosen target FPGA device. pcie_mini still needs the Xilinx PCIE Endpoint block and the GTP transceivers......
Development status: Beta
License: LGPL
Updates:
Apr 26, 2011: Descrition and status update: v1.1 fixes bugs with 8/16-bit transactions and with consecutive single transactions. Apr 25, 2011: spec update: WBC Apr 24, 2011: added description for new project

Generic AHB master stub
Generic AHB master stub. Built out of an AXI master and an AXI2AHB bridge. Supports 32/64 data bits, AHB bursts and random wait-states. The design is built according to input parameters: address bits, data bits, etc.
Development status: Alpha
License: LGPL
Updates:
Apr 27, 2011: Initial files upload

Generic AHB slave stub
Generic AHB slave stub. Supports 32/64 data bits, AHB bursts and random wait-states. The design is built according to input parameters: address bits, data bits, etc.
Development status: Alpha
License: LGPL
Updates:
Apr 27, 2011: Initial files upload

Generic APB master stub
Generic APB master stub. Based on an AXI master stub and an AXI2APB bridge. Supports both APB and APB3 protocols (APB3 is with pready and pslverr signals). The design is built according to input parameters: address bits, protocol type, etc.
Development status: Alpha
License: LGPL
Updates:
Apr 22, 2011: Initial files upload

Generic APB slave stub
Generic APB slave stub. Support both APB and APB3 protocols (APB3 is with pready and pslverr). Supports slave error, random and fixed wait-states. The design is built according to input parameters: address bits, protocol type, etc.
Development status: Alpha
License: LGPL
Updates:
Apr 22, 2011: Initial files upload

Generic AXI master stub
Generic AXI master stub. Supports multiple internal masters (multiple AXI IDs), 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: ID number, data bits, AXI command depth, etc.
Development status: Alpha
License: LGPL
Updates:
Apr 19, 2011: description Apr 5, 2011: uploaded files Apr 4, 2011: moving to verification catagory

Generic AXI slave stub
Generic AXI slave stub. Supports 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: address bits, data bits, AXI command depth, etc.
Development status: Alpha
License: LGPL
Updates:
Apr 19, 2011: description
Apr 5, 2011: Initial files upload


Johan Rilegård, ORSoC


© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.