OpenCores

OpenCores.org

NEWSLETTER JANUARY 2011

www.orsoc.se

Extended CV functionality

Now it is possible for our users to upload a full CV documentation and also to specify detailed experiences/competences...

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OpenCores at linux.conf.au 2011

ORSoC and OpenCores will be represented at the linux.conf.au 2011 Open Day in Brisbane, Australia, on Saturday January 29....

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IP feedback system

Automatic feedback system will improve the statistics presented for all IP cores.

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OpenCores.org - translated to Chinese

Since a large percentage of OpenCores users are from China, we have translated the common pages on OpenCores to Chinese...

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Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
- Replaced a broken power-supply.
- Added two new website functions

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New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

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Newsletter January 2011


OpenCores adds extended CV functionality

OpenCores want to help our users/community to find new exciting job or consultant opportunities.

We have therefore added the possibility for our users to upload a full CV documentation and also to specify detailed experiences/competences.

This service is both meant for engineers that are actively looking for a new job, or engineers that just wants to scan/subscribe the market for the "dream" opportunity, or for consultants that are looking for new assignments.

We hope that this functionality will enable us to help you find your "dream" position. So go to the "my-account"-page and select the "Extended profile" shortcut. Or use the link below:

"Extended profile"-page

Marcus Erlandsson, ORSoC





OpenCores at linux.conf.au 2011

ORSoC and OpenCores will be represented at the linux.conf.au 2011 Open Day in Brisbane, Australia, on Saturday January 29.

Attending will be a member of the OpenRISC development team who will be demonstrating and discussing the platform.
All those nearby are encouraged to come along to the open day of this notable conference.

For more information see the LCA2011 site: http://lca2011.linux.org.au/programme/open_day

Also note that the original venue, as listed on the above page, is subject to change, so please double check before coming along!

Thanks

Johan Rilegård, ORSoC





OpenCores adds IP feedback system

OpenCores proudly announce the "IP feedback system", a system that automatically sends an email after two weeks to a user that has downloaded an IP cores, asking for feedback. This functions will help us improve the statistics presented for all IP cores.

And as you know, "good" statistics for open-source IP cores are critical in order to achieve credibility.

With this system we will be able to remove "incorrect" statistics, for example, when users have downloaded an IP core to the temp-directory and didn't have time to look at it right away, this often means that it never got used. Our system will identify these "invaild statistic"-hits and will remove them from the presented statistics.

We would also like present more detailed information about how the IP core is used (hobby, commercially, FPGA, ASIC etc). This information will of course not be presented directly onto the website, it will be summarized and bundled together with information from all users.

So please help us improving the quality and statistics on OpenCores by answering on a few questions send via email two weeks after your download.

Marcus Erlandsson, , ORSoC





OpenCores translated to Chinese

Since a large percentage of OpenCores users are from China, we have translated the common pages on OpenCores to Chinese.

The selection is done on the first page and we hope that this will help the Chinese users to get started easier and enable more engineers to join the open-source movement.

Note that all "project"-pages must still be presented in English to enable a world wide usages.

Marcus Erlandsson, , ORSoC





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Large backend system upgrade of software
  • Added two new functions (Extended CV, IP-feedback-system)


Server information:

  • Increase storage capability.
  • Replaced a broken power-supply.


Our message to the community:

  • Please make sure your personal information under the "My Account"-page, is up to date.
  • Upload you CV and competence information using the "Extended CV" function in the "my-account"-page.

Marcus Erlandsson, ORSoC





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

Ray Tracing Arithmetic Engine
Ray Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General. The Main Goal of this project is to create an engine to Render 3D models. This engine is made over HW/SW. What Im planning to do is to make a RTL generic enough to plug it along with a processor, by means of a bus or any connector the developer wishes. So the RTL's published on this page will describe the HW part of the engine. I don't know, YET, if I'm allowed to upload SW source code. If I am, for sure I will, but if not a proper project page will be set on the next days. I will publish, as mentioned, the soruce code for a NIOS II processor, and that will be the Rendering Engine SW portion. So, what I expect is to achieve a simple HW portion of the Rendering Engine, that serves on its original purpose -a Ray Tracing Rendering Engine- but in the near future, I would hope to see the engine to be used for General Purposes.
Development status: Planning
License: LGPL
Updates:
Jan 13, 2011: What I Want To Do?

FPGA Communication Framework
FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a host-software library/API (Java and C++). It enables a host PC to transmit data at 120 Mb/s to XIlinx-based FPGA boards via Ethernet using standard internet protocols (UDP/IP). A custom lightweight connection-oriented protocol guarantees reliability. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all ICAP functionality. The core also provides an extensible user-channel interface and provides up to 15, 8-bit user-data channels that can be connected to user circuitry (configurable by the user). The host software API supports both Java and C++ and provides high-level functionality for making connections and transmitting data.
Development status: Planning
License: LGPL
Updates:
Jan 14, 2011: added description

IEEE 802.15.4-PHY Core
This core implements the transmission and reception paths described in [1]. The reception part needs to be re-designed and adapted to the chosen RF front-end in terms of frequency estimation, phase correction and chip/symbol synchronization techniques which are not implemented in this version.
Development status: Alpha
License: GPL
Updates:
Jan 10, 2011: Editing project info.
Jan 9, 2011: Editing project webpage.
Jan 8, 2011: Editing webpage.
Jan 8, 2011: Editing core webpage.
Jan 8, 2011: Editing project website

tiny SPI
This is an 8 bits SPI master controller. It features optional programmable baud rate and SPI mode selection. Altera SPI doesn't support programmable rate which is needed for MMC SPI, nor does Xilinx SPI.
It is small. It combines transmit and receive buffer and remove unused functions. It takes only 36 LEs for SPI flash controller, or 53 LEs for MMC SPI controller in an Altera CycoloneIII SOPC project. While Altera SPI takes around 143 LEs. OpenCores SPI takes 857 LEs and simple SPI takes 171 LEs.
It doesn't generate SS_n signal. Please use gpio core for SS_n, which costs 3- LEs per pin. The gpio number is used for the cs number in u-boot and linux drivers.
Development status: Beta
License: LGPL
Updates:
Jan 9, 2011: tiny_spi core takes 53 LEs for mmc spi controller on Altera CycloneIII. Driver available for u-boot and linux.

Uart (FIFO cpu interface) with SV Self-Checking Testbench
This is a fully synchronous (single clock domain, no asynchronous resets) UART with a FIFO buffered cpu interface and a SystemVerilog transaction based self-checking testbench. The VHDL RTL is written in a "single process" style to improve code readability and lets the synthesis tool infer the flops and gates.

The cpu interface is simple (address, data in, data out, read enable, write enable).
Transmit and receive FIFO size is configurable with a generic.
Baud rate is register programmable.
Currently only support no parity bit, 8 data bits and 1 stop bit (N81).

Development status: Planning
License: LGPL
Updates:
Jan 3, 2011: Added inital version of UART RTL and SV testbench source code. Source and testbench compile without error, but not debugged in the simluator yet.


Johan Rilegård, ORSoC



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