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NEWSLETTER OCTOBER 2010

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OpenRISC 1200 based platform - highly popular

ORSoC has been out promoting this platform for a while now and we get extremely positive response from many different customers, within various segments

Read more...


Verilator - a fast cycle-accurate Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.

Read more...


New OpenCores servers

The OpenCores community is constantly growing both in numbers of registered users (reaching 100.000 within days) as well as in traffic-load and activities in the different forums, forcing ORSoC doing major system upgrades to meet the growing demand

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
- Removed 70 "old" projects that didn't contain any design files.
- Started the two new i7-servers hosting OpenCores.
- Moved the server to a new location.
- Upgraded Internet connection to dedicated 10/10Mbit fiber.

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

Read more...


Three bits per memory cell

A FLASH memory which handles three bits per memory cell and store as much as 8 GB
That is what the Korean Samsung have just started producing

Read more...


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Newsletter October 2010


OpenRISC 1200 based platform - highly popular

Last month we presented the OpenRISC based platform ORSoC has put together. The platform includes the OpenRISC 1200 processor, some peripherals, running latest Linux and busybox.

OpenRISC1200 platform, based on OpenCores IPs, supported by ORSoC

ORSoC has been out promoting this platform for a while now and we get extremely positive response from many different customers, within various segments (i.e. industrial, network, communication, space and R&D).

There are many reasons for its popularity. A important aspect is of course that it is based on true open source IPs, which gives the customers full control of the design. But just as important is the availability of a bleeding edge, state of the art, tool chain which gives smooth development projects. Another thing that is of huge importance is that the customer has a commercial partner with extensive experience from SoC designs based of the “OpenCores-technology”. ORSoC offer professional support to the technology and platform as well as services to customize the platform for specific functions/applications and make sure it fulfills the requirements set for the products.

During our work in different customer projects (customizing the platform) we always get positive feedback from the extensive verification possibilities that are offered to this technology. ORSoC has developed a unique verification methodology that gives us the possibility to verify the design from many different approach angles. This also gives the option to start develop SW in parallel with the hardware.

We are absolutely sure this technology will be adopted by more and more product developers’ world wide and we are ager to help new customers develop their future products based on this fantastic technology.

For more information about the platform please visit our website ORSoC/platform

For more information about our verification methodology or our design service, please contact us at info@orsoc.se

Johan Rilegård, ORSoC





Verilator - a fast cycle-accurate Verilog simulator using C++/SystemC

Cycle accurate models in C++ and SystemC are becoming an increasingly important part of the developing a SoC design (System-on-Chip), especially when using soft-processors with embedded software/operating systems. These systems requires more simulation performance then traditional event-driven simulatorns can offer. The solution is to translate the synthesizable Verilog RTL into a cycle accurate C++ and SystemC simulation model.

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Verilator supports the synthesis subset of Verilog, plus initial statements, proper blocking/non-blocking assignments, functions, tasks, multi-dimensional arrays, and signed numbers. It also supports very simple forms of SystemVerilog assertions and coverage analysis. Verilator supports the more important Verilog 2001 constructs, with additional constructs and SystemVerilog support added as users request them.Verilator has been used to simulate many very large multi-million gate designs with thousands of modules. Verilator is a growing body within the "Free EDA Software" community and is now maintained by Wilson Snyder.

It does not offer a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator, Verilator should be used as a complement.

Performance
Verilator does not simply convert Verilog HDL to C++ or SystemC. Direct translation alone is fairly easy (and was what Verilator abandoned over 5 years ago). Rather than translate, Verilator compiles your code into a much faster optimized model, which is in turn wrapped inside a SystemC module. The results are a compiled Verilog model that executes over 10x faster than standalone SystemC.

Verilator is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Verilator has about the same performance as the leading commercial Verilog simulators including Carbon Design Systems Carbonator, Modelsim, Cadence NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC, but is free, so you can spend on computes rather than licenses. Thus Verilator gives you more cycles/dollar than anything else available.

Here's how Verilator stacks up to some of the other commercial and free Verilog simulators:

Verilog Simulator Benchmarks Below are the results from running small Verilog model through several standard simulators. As with any benchmark mileage varies; this example's performance will not match your design's results. Verilator and VTOC are cycle based simulators, while the others are activity driven. If a design is only being clocked, Verilator will perform worse when compared, and vice versa. The example below is between the extremes.

Results

  • 1,420,000 SuSE 11.1 64-bit (Free) Verilator 3.714; gcc 4.3.2 -O3 -m64
  • 1,170,000 SuSE 11.1 32-bit (Free) Verilator 3.714; gcc 4.3.2 -O3 -m32
  • 814,000 SuSE 11.1 64-bit Cadence NC-Verilog 8.20-s013 +nc64bit
  • 799,000 SuSE 11.1 32-bit Cadence NC-Verilog 8.20-s013
  • 510,000 (1) FC 8 32-bit Pragmatic-C CVC 4.17b 32-bit +nbaopt
  • 468,000 (1) FC 8 32-bit Pragmatic-C CVC 4.17b 32-bit
  • 407,000 (1) FC 8 64-bit Pragmatic-C CVC 4.17b 64-bit
  • 403,000 (1) FC 8 64-bit Pragmatic-C CVC 4.17b 64-bit +nbaopt
  • 473,000 SuSE 11.1 32-bit Synopsys VCS C-2009.06
  • 442,000 SuSE 11.1 64-bit Synopsys VCS C-2009.06 -full64
  • 80,600 (2) Windows 2000 32-bit Veritak 2.20X
  • 17,800 SuSE 11.1 64-bit (Free) Icarus Verilog 0.9.1
  • 13,400 (2) Windows 2000 32-bit MXE
  • 11,600 (3) SuSE 11.1 64-bit (Free) GPL CVer 2.12a
Software: SuSE Linux 11.1, Kernel 2.6.27, GCC 4.3.2.
Hardware: AMD Phenom 9500 2.2GHz, DDR2 667 Memory. Note Intel processors seem to have a smaller 32 vs 64-bit performance difference.
(1) CVC numbers were reported by www.pragmatic-c.com; their numbers have been normalized from a run on Core2 Duo hardware.
(2) Veritak and MXE numbers were reported by www.sugawara-systems.com; their numbers have been normalized from a run on older hardware.
(3) GPL CVer 2.12a requires commenting out v_ex.c line 4022 "__my_free fiopfp..." to avoid a coredump. To our knowledge, CVer has been unsupported since 2005.

Other Users Benchmarks Again: As with any benchmark mileage varies; this example's performance will probably not match your results.

Other users have reported the following relative performance on their designs: (Note they seem contradictory, as they refer to differing designs.)

  • Verilator is 90x faster than Icarus Verilog.
  • Verilator is 10-40x faster than Modelsim SE.
  • Verilator is 3x faster than NC-Verilog.
  • Verilator is 1.5x faster than VCS.
  • VTOC is 4x faster than Verilator.
  • VTOC is 50x faster than NC-Verilog.
  • VCS is 3x faster than Verilator.
  • VCS is 3x faster than NC-Verilog.
  • VCS is 10x faster than NC-Verilog.
  • VCS is the same speed as NC-Verilog.
  • CVer is the same speed as Icarus Verilog.

Third party usages Verilator is used heavily within the OpenRISC project at OpenCores and also within ORSoC, it's truly a excellent tool and we highly encourage people to start using it and to help Wilson Snyder and his team with verification and development. I'm sure that they are happy to get more contributers on board.

More well-known companies that are/has used Verilator (based on user correspondence, not official statements): ARM, AMD, BROADCOM, CSR, INFINION, RAYTHEON, SUN, NXP and many more.

Marcus Erlandsson, ORSoC





OpenCores community grows - forcing major system upgrades

The OpenCores community is constantly growing both in numbers of registered users (reaching 100.000 within days) as well as in traffic-load and activities in the different forums, forcing ORSoC doing major system upgrades to meet the growing demand. ORSoC has added two more I7-servers to handle the increasing system load and we have also moved to a new server location providing improved uptime.

The Internet connection has also been upgraded to a 10/10Mbit dedicated fiber connection, making sure that the response time and bandwidth is sufficient for the OpenCores users.

ORSoC hope that these improvements will be appreciated by the community and that we together can continue contributing to open-source hardware. We would like more of our users to help the project maintainers both with development as well as verification, and of course providing feedback about how the IP-cores are being used in the end-product. Together we can change the way electronic-products will be developed, but it means that we all must "pitch in" to achieve this, so join us and please send us ideas on how to make OpenCores better (oc-team@opencores.org).

Marcus Erlandsson, ORSoC





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Removed 70 "old" projects that didn't contain any design files.


Server information:

  • Started the two new i7-servers webserver hosting OpenCores
  • Moved the server to a new location
  • Upgraded Internet connection to dedicated 10/10Mbit fiber


Our message to the community:

  • Please try to upgrade your projects to reach the OCCP level.





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

Maximum/Minimum binary tree finder
The aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where number of entries = N, can be configured at compile time and also the width = M of each entry.
Development status: Beta
License: LGPL
Updates:
Oct 5, 2010: Description
Oct 5, 2010: start using the project

mod3_calc
A quick & simple mod 3 calculator(only just combinational logic). the input 8-bit data is divided by 3. and the output is only 0, 1, or 2. I use XilinxISE10.1 Synthesis the file, the speed can reach 113MHz.
Development status: Alpha
License: LGPL
Updates:
Oct 11, 2010: description add

DVB-T transmitter with FPGA device
The DVB-T Standard is published as EN-300744. This project implements a non hierarchical transmitter with the parameters FEC=3/4, QAM=64, OFDM=2k, GI=0 corresponding to the example including at the communications toolbox of Simulink.
Development status: Stable
License: LGPL
Updates:
Sep 29, 2010: description_v2
Sep 29, 2010: description

AVR HP, Hyper Pipelined AVR Core
The project is based on OpenCores' AVR project by Ruslan Lepetenok.
The core is now hyper pipelined. It is a technique to multiply the functionality of a design by adding registers (called pipeline stage registers) to the core logic in order to multiply its functionality.
The functional behavior of the AVR remains the same, the hyper pipelined version is used when multiple, equal AVR cores (2, 3, ...) are instantiated in the design (multicores).
The main benefit is the multiplication of the core's functionality by only implementing registers. This leads to a reduced size compared to the individual instantiation of the cores. This is a great advantage for ASICs but obviously very attractive for FPGAs with their already existing registers.
Another issue is the performance of the resulting hyper pipelined AVR core. The pipeline stage registers are timing driven placed to partition the critical path into equal parts, which leads to an almost multiplied performance of the design. The timing is optimized for a Spartan 3 and a Virtex 5 device from Xilinx.
The modifications are done on RTL, so that the project can be used in an RTL based testbench.
The project shows the modified RTL code with 2, 3 and 4 times multiplied functionality. It is delivered with a testbench and a detailed documentation.


Development status: Stable
License: LGPL

OpenRisc 1200 HP, Hyper Pipelined OR1200 Core
The project is based on OpenCores' OR1200 project.
The core is now hyper pipelined. It is a technique to multiply the functionality of a design by adding registers (called pipeline stage registers) to the core logic in order to multiply its functionality.
The functional behavior of the OR1200 remains the same, the hyper pipelined version is used when multiple OR1200 cores (2, 3, ...) are instantiated in the same design (multicores).
The main benefit is the multiplication of the core's functionality by only implementing registers. This leads to a reduced size compared to the individual instantiation of the cores. This is a great advantage for ASICs but obviously very attractive for FPGAs with their already existing registers.
Another issue is the performance of the resulting hyper pipelined OR1200 core. The pipeline stage registers are timing driven placed to partition the critical path into equal parts, which leads to an almost multiplied performance of the design. The timing is optimized for a Virtex 5 device from Xilinx.
The modifications are done on RTL, so that the project can be used in an RTL based testbench.
The project shows the modified RTL code with 2, 3 and 4 times multiplied functionality. It is delivered with a testbench and a detailed documentation.
Development status: Stable
License: LGPL

z80control
Microprocessor targeting embedded industrial control systems. Uses a z80 core available at opencores as T80. It is in early development stages. It is currently being developed with a Altera Cyclone II FPGA Starter Board (DE1). The idea is to have a system that will communicate to a PLC and a PC via serial interface. This allows the ability to expand peripherials on a PLC while giving the user PC control from a visual enviroment using custom software.
Development status: Alpha
License: GPL
Updates:
Oct 1, 2010: Description
Sep 28, 2010: Lisencing


Johan Rilegård, ORSoC



Three bits per memory cell

A FLASH memory which handles three bits per memory cell and store as much as 8 GB. That is what the Korean Samsung have just started producing. Recently, Intel and Micron boasted that they were the first to sample with the same storage capacity and technology - but their volumes will have to wait to the end of the year.

Common for Samsung and the two partners Intel and Micron is that they managed to develop NAND flash memory that can store 64 Gigabit or 8 Gbytes, and that they all use a technology that stores three bits per memory cell.

The difference is that Intel and Micron are running in a 25 nm process, and the duo so far only offers samples. Volumes will be towards the end of the year, claiming the companies. Samsung claims to have however already started production and the process used is called 20 nm-class.

Intel and Micron already has a memory of 25 nm which store 8 Gbytes, but it only stores two bits per cell. New additions, which store three bits per cell, is 131 square millimeters, which according to the two companies means that it is 20 percent smaller than its predecessor.

How large area Samsung's newly launched 8 GB memory occupies is not revealed.

Neither reveals Samsung, Intel, Micron, or how many times their memories that store three bits per cell can be written before it degrades. However, all three agreed that the new memories will take place in future USB applications, SD memory card and other consumer electronics.

Published by Elektroniktidningen at www.etn.se/52278


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