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NEWSLETTER SEPTEMBER 2010

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OpenRISC - Bleeding edge GNU toolchain

The latest release of work that has updated the OpenRISC processor toolchain.
The update will see an approximately three year gap bridged for the OpenRISC toolchain ports and libraries, with both being bought up to bleeding edge versions

Read more...


OpenRISC 2000 Project Launched

The OpenRISC 2000 (OR2K) is starting to define a new architecture for modern high performance FPGAs.
Drawing on the experience of the OpenRISC 1000 project, the new architecture will be designed from the outset for multi-core usage and will offer improved performance and code density. The emphasis will be on modularity of design, to give maximum flexibility to the end user.

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
- Website optimization
- Added new products to the webshop

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

Read more...


OpenCores IP goes into Space

Satelite product based on OpenCores technology A satellite computer, built on the OpenRISC1200, will be launched up in space in the spring of 2011.
AAC Microtec has developed a space-qualified version of the 32-bit processor core OpenRISC1200. The design has been developed by ORSoC in cooperation with FMV, NASA and U.S. armed forces, and will sit in a communications unit/computer which will have the first flight in a satellite in April

Read more...


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Newsletter September 2010


OpenRISC Announcement - Bleeding edge GNU toolchain.

The OpenRISC team from OpenCores and ORSoC are very pleased to announce the latest release of a set of work that has focused on updating the OpenRISC processor toolchain.

The included tools are currently:

  • GNU binutils 2.20.1
  • GNU GCC 4.5.1
  • GNU GDB 7.2
  • uClibc 0.9.29
  • newlib 1.18.0
  • Linux 2.6.34
  • BusyBox 1.7.5
  • or1ksim 0.5.0 (Architecture simulator)


It is now also possible to intall the OpenRISC toolchain through Launchpad.net's platform.

That means Ubuntu users can install the toolchain using the aptitude tool.

Currently there are builds for Ubuntu 10.04 LTS Lucid Lynx and 10.10 Maverick Meerkat available. Potentially 9.10 might be supported, 9.04 is less likely to be supported. Both 32-bit and 64-bit versions are available.

The following steps show how to add the package repository and install it:
$ sudo add-apt-repository ppa:openrisc/openrisc
$ sudo aptitude update
$ sudo aptitude install binutils-openrisc gcc-openrisc

At present the GCC does not contain any extra libraries such as newlib or uClibc, but it is expected coming versions will contain at least newlib.


The update will see an approximately three year gap bridged for the OpenRISC toolchain ports and libraries, with both being bought up to bleeding edge versions.

The updates are in their final stages of testing in simulation and on hardware, and are now available at OpenCores.

By enabling support for the latest and greatest from the world of open-source OSes and libraries for the OpenRISC platform we hope to see increased uptake and participation in the project from all. The team at OpenCores are forever tweaking and improving parts of the implementations that exist, allowing them to be used with greater ease and reliance.

We hope to generate further interest in the OpenRISC project, and potentially gain new contributors and supporters of the platform. We expect that by updating the port for the Linux kernel and supporting software that we will see increased uptake of the technology and greater participation from the community. As well as this, we hope to release further tools and documentation that will help people get started with the OpenRISC platform.

There are always problems inherent in aiming for software reuse, however the combination of reusable IP and driver software essentially results in a two-for-one deal. Considering the attention the software development receives in modern designs, it's good to know that when using highly portable open-source IP and low-level drivers, they start off on an effective and dependable note.

Stay tuned for further news of the release of the kernel and much more!





OpenRISC 2000 Project Launched

The OpenRISC 2000 (OR2K) is starting to define a new architecture for modern high performance FPGAs. Drawing on the experience of the OpenRISC 1000 project, the new architecture will be designed from the outset for multi-core usage and will offer improved performance and code density. The emphasis will be on modularity of design, to give maximum flexibility to the end user.

As with the OpenRISC 1000, OpenCores commitment to openness combined with flexibility will be ensured by licensing the OR2K under the GNU Lesser General Public License (LGPL).

Some of the design decisions taken so far include a re-working of the instruction set, aimed at striking a better balance between code-density and simple RISC-like implementation. Future areas for work include interrupt handling, floating point interface, and software debug interface.

The project's page is implemented as a Wiki, a first for OpenCores, offering a simple and effective tool for group collaboration. The main page includes a suggestions page for community suggestions, comments and questions.

The architectural specification (also on the Wiki) is based on the OpenRISC 1000, and is being reviewed and updated for the OR2K. Each section of the architecture spec. has its own discussion page, where suggestions for changes can be made. The most active work at present is in on the .

If you would like to get involved, add your suggestions to the Wiki, post your suggestions on the or join in the discussion using IRC at freenode.net, channel #opencores.





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Solved some minor bugs
  • Removing "old" projects that doesn't contain design files


p> Server information:
  • Purchased two new i7-servers in order to live up to the increasing interest of OpenCores


Our message to the community:

  • Please try to upgrade your projects to reach the OCCP level (OpenCores Certified Projects), read more about what is needed of your project to achieve this in FAQ-Projects
  • Please make sure that all design-files including documentation are stored the project SVN repository. The "Downloads" page is only meant for pictures or document that are intended to be visible on the "Overview"-page. No design-files are allowed on the "Downloads" page





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

During the last month, 11 (!!!) new projects started. But unfortunately most of them have not done a proper description of the project and some have not yet checked in any files. Without this info they do not qualify into this section of the newsletter.

This means we only have 2 new poject that have reached "first stage" of development.

Versatile library
A Verilog HDL library with frequently used functions. Care have been taken to fully support synthesis of all modules. Different versions exist for optimal synthesis support. Currently ACTEL and ALTERA are supported.
Development status: Alpha
License: LGPL
Updates:
Sep 14, 2010: added more modules
Sep 1, 2010: Project created

Status LED
A simple module to get the most of your on board heartbeat LED. Change or add more sequences easily in parameters file.
Development status: Stable
License: LGPL





OpenCores IP’s goes into Space

Satelite product based on OpenCores technology

Open Source IP cores from OpenCores, for implementation in FPGAs or ASICs, experience an increasing number of users and projects. Swedish AAC Microtec is one good example - their satellite computer, built on the OpenRISC1200, will be launched up in space in the spring of 2011.

A year ago, there were 670 projects on the open source forum opencores.org, today there are some 800. The site now has almost 100 000 registered users, and between 2500 and 3000 are added every month. These numbers illustrate how the use of open source IP blocks is increasing.

- Attitudes are also changing. Not long ago many users at large companies used hotmail or gmail addresses for registration and on the forum. But now, it is more common to use their business addresses, - says John Rilegård who is president of ORSoC, the Swedish consulting company that operates and maintain OpenCores.

The number of customers who openly says that their projects using open IP blocks also increases, in such diverse industries as aerospace, physics research, telecom and industrial electronics, he says.

- Often, it is the end customers that require open source. For cost reasons, of course, but also for quality reasons. Some of the open IP blocks are among the best verified in the world, "says Marcus Erlandsson, CTO at ORSoC.

Such a user is AAC Microtec, who developed a space-qualified version of 32-bit processor core OpenRISC1200. The design has been developed by ORSoC in cooperation with FMV, NASA and U.S. armed forces, and will sit in a communications unit/computer which will have the first flight in a satellite in April.

- The current space processors are often very expensive, they can cost one million to license. Our mission was crystal clear - cut costs. So therefore we have chosen to use open source as far as possible, "says Fredrik Bruhn at AAC Microtec.

His company has added space tolerant protection to the customized processor platform (delivered by ORSoC). They have also included wider data buses and hardware that corrects errors in real time. Together with ORSoC they have also gone through the whole kernel, added improvements, and returned the result to OpenCores.

- What we did does not affect processor performance, and our core, Openrisc32-FT (fault tolerant) can use exactly the same compiler and Linux versions, - says Fredrik Bruhn.

One difference is that the fault-tolerant core occupies almost twice as much resources in an FPGA. Which means that the surface will be twice as large, and consume around twice as much power.

With the communication module that AAC is building based on the processor, the company tries to create a new level of "plug & play" in the space context. Equipment that will communicate with the module need only to write their own drivers, in XML. AAC's computer then automatically configures the system.

Satelite product based on OpenCores technology
The development platform, based on the OpenRISC1200, developed by ORSoC, contains in addition to the processor a number of peripheral cores, tools and operating system (Linux) for both software development and FPGA or ASIC implementation. It can be customized with OpenCores IP as well as proprietory IP, and can of course be reused in future projects.

- We create the operating system "on the fly” and automatically configure all the satellite's functions, - says Fredrik Bruhn.

In a separate project, AAC has adapted a completely different processor for space, a small PIC16 core which also is derived from OpenCores. This processor sits on a small card with the AD and DA converters and is used to collect data from sensors to ensure that the satellite is functioning properly. The entire card consumes only 200 mA.

- We have re-written the kernel for radiation and fault tolerance. And at the same time we've made it faster - usually PIC16 is running four clock cycles per instruction, but our version runs one instruction per clock cycle, says Fredrik Bruhn.

An important fact for AAC and other clients to chose OpenRISC and other open IP blocks from OpenCores is the advent of proper development tools, ready to use platforms that can be customized, and that much work is done on the kernel to use the latest version of Linux, currently 2.6.34.

- We have put a lot of work into ensuring the ecosystem, with professional support and design services, and we are confident that this is a major reason for the technology's increasing popularity, says John Rilegård.

A part of the ecosystem is the quality assurance on OpenCores that has been lifted to a new level. Nowadays many IP blocks feature structured revision management, where all the versions, all documentation and all test benches for each version are properly handled. The projects may also apply for an OCCP labeling, Open Cores Certified Project, which according to ORSoC is at least as good a hallmark of quality as commercial IP blocks offer. So far, a dozen IP blocks have applied for such certification, one of course being the OpenRISC1200.

The core OpenRISC1200 is also accelerating in terms of speed.

- The record to date is 293.8 MHz in an existing FPGA, a Xilinx Virtex 5, - says Marcus Erlandsson.

Work on the next version, called OpenRISC2000, has also begun. The architecture specification is being refined, and ORSoC expects a first release toward the spring.

- It is designed for multi-processor implementations, and is even more modular than OpenRISC1200. Users can add and remove individual instructions, said Marcus Erlandsson.

Published by Elektroniktidningen at www.etn.se/51987


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