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NEWSLETTER AUGUST 2010

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Implementation statistics for all OpenCores IP's

Before the summer we launched the new service that implements any Verilog/VHDL IP core across popular FPGAs/CPLDs, and tells developers which programmable logic devices meet their IP's requirements like size, speed and power consumption.
implementation stastistics, OpenCores.org
Make sure to use the service on your project...

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New products in the webshop

There are new products in the webshop. Make sure to check them out.
If you have a product you would like to promote via OpenCores webshop, please let us know...

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Commercial companies contributes back to OpenCores

Many commercial companies contributes back to OpenCores with the IPs after bugfixing/improvements. ÅAC Microtech (a hi-tech company within the space industry) is just one example....

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Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
- Website optimization
- Added new products to the webshop

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New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

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Newsletter August 2010


Commercial companies contributes back to OpenCores

ÅAC Microtec is an internationally acknowledged leader of developing, manufacturing and marketing miniaturized and robust multi-functional electronics systems.

ÅAC Microtec use IP-cores from OpenCores. When using these IPs in their designs, they have fixed bugs and added improvements. ÅAC will contribute back the modified RTL-code for these bug-fixes and improvements they have added. This is a brilliant example that shows how open-source hardware development should work, meaning that the original developer/developers get help with verification which requires a huge workload to execute.

This is just one example of all parties that uses and contributes back to OpenCores, but we still would like to highlight this and encourage all users to contribute back with the improvements of all blocks that is used.





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Website optimization which made the system faster
  • Added new products to the webshop


Server information:

  • The servers has been running smoothly


Our message to the community:

  • Please try to upgrade your projects to reach the OCCP level (OpenCores Certified Projects), read more about what is needed of your project to achieve this in FAQ-Projects
  • After your project has reached the OCCP-level, you can apply for "Extended Implementation Statistics". This service is available from Plunify and its a web service that implements any Verilog/VHDL IP core across popular FPGAs/CPLDs, and tells developers which programmable logic devices meet their IP's requirements like size, speed and power consumption. Such data helps developers quickly obtain working designs on as many FPGAs/CPLDs as possible





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

Anti-Logarithm (square-root), base-2, single-cycle
A fast (single-cycle) base-2 antilog function.
Development status: Stable
License: LGPL
Updates:
Aug 8, 2010: 1st try uploaded

LFSR-Random number generator
The lfsr core is a random number generator based on linear feedback shift register(LFSR). The sequence generated has the maximum length possible.The period of sequence generated by a n-bit LFSR is equal to 2^n-1.The tap values used are supposed to create maximum length sequence.
Development status: Alpha
License: LGPL
Updates:
Aug 17, 2010: output_enable input is removed from the port list.Setting the seed is made synchronous instead of asynchronous.
Aug 1, 2010: The vhdl codes where uploaded and the project is in alpha stage.
Jul 31, 2010: Planning completed on 28th July 2010

DMX512 transceiver
•DMX protocol fully implemented in hardware
•DMX channels simply mapped in CSR address space
•Thru mode enables operation as a traditional DMX receiving device
Development status: Alpha
License: GPL
Updates:
Aug 13, 2010: More info
Aug 8, 2010: initial description

OHCI Full/Low-Speed USB Host Controller
•Supports full (12Mbps) and low (1.5Mbps) speed operation
•Two downstream ports with shared bandwidth
•Integrated PHY
•Directly interfaces to common USB transceivers such as the MIC2550A
•Hybrid architecture featuring the Navré AVR compatible processor (8-bit RISC) to implement the complex parts of OHCI in C software.
•Two asynchronous clock domains: system clock and 48MHz USB
•AVR program and OHCI descriptors and data are stored in shared (system addressable) on-chip dual-port RAM
Development status: Alpha
License: GPL
Updates:
Aug 7, 2010 Added CSR link
Aug 5, 2010 Initial description
Aug 5, 2010 Initial description

PLB-to-WB Bridge
The intention of the project is the development of a bus bridge, which enables the usage of WB compliant IP cores in a system, which uses the Processor Local Bus (PLB) as system and peripheral bus. The PLB-to-WB (PLB2WB) Bridge enables the access to slaves on the WB side for masters on the PLB side.
Features:
- separate clock domains for PLB and WB
- separate resets for PLB and WB possible - PLB address pipelining (optional)
- PLB fixed length burst transfers (only words, optional)
- PLB line transfers (optional)
- WB B.3 classic cycles (block and single, block cyckes are optional)
- flexible address offset
- handling of delayed write errors on WB side - transfers interrupts to PLB side
Development status: Alpha
License: LGPL
Updates:
Aug 15, 2010: Added the svn path to the file and folder description
Aug 14, 2010: added some points to the 'Features' list
Aug 14, 2010: corrected some spelling mistake
Aug 13, 2010: Added information about development status
Aug 13, 2010: Added information about file and folder structure
Aug 13, 2010: basic info

SPI serial DAC interface
An implementation of serial Linear Technologies LTC2624 Quad 12bit DAC using SPI 32bit data transfer method. The core is FPGA proven, works on Spartan-3E Starter Kit.
Development status: Stable
License: LGPL
Updates:
Aug 6, 2010: Core specification updated.

Navré AVR clone (8-bit RISC)
•Atmel AVR compatible
•All Classic Core instructions implemented, except conditional branches on I/O registers
•No interrupt support
•Interrupt related instructions behave as if the I (interrupt enable) bit is hardwired to 0
•Verilog-2001
•Used to control the SoftUSB OHCI USB host•Fully synchronous
•2-stage pipeline
•Almost cycle accurate with the original AVR. Most instructions execute in 1 cycle.
•Synthesis results (ISE 12.2 default, post performance evaluation P&R, XC6SLX45-2): 1K LUTs, 11.7ns (85MHz) clock period
Development status: Beta
License: GPL
Updates:
Aug 7, 2010: Status
Aug 5, 2010: testing
Aug 5, 2010: Initial descriptionj

FastMemoryLink VGA framebuffer controller
•Minimal VGA framebuffer core
•RGB565 16bpp
•Directly drives a 3x8-bit DAC and sync signals.
•Fully configurable timings and resolution
•Multiple buffering support with buffer switch during the blanking interval to prevent tearing artifacts.
•Milkymist CSR and FML bus interfaces.
•Two asynchronous clock domains - VGA and system.
•Bit-banged DDC interface.
Development status: stable
License: GPL
Updates:
Aug 7, 2010: status
Aug 7, 2010 Initial description





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