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NEWSLETTER FEBRUARY 2010

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Synthesize ORPSoC

We're happy to announce that the ORPSoCv2 project now include scripts enabling it to be synthesized for FPGA. Although this first release contains support for a single Xilinx development board, we encourage...

Read more...


Apply for "OpenCores Certified Project"-logo

Highlighting projects and maintainers that deliver quality open-source IP-cores, meaning projects that are 100% completed and includes all needed items...

Read more...


How good are high-level synthesis tools for FPGAs?

In theory it looks very tempting. An expert in DSPs just needs to take their C code and a high-level synthesis tools to get to the world of FPGAs where parallelism gives (almost) unlimited performance for a small fee. In reality, it is not so easy...

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
- OpenCores menu system has been redesignedr
- Database access has been optimized.

Read more...


10 new IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
Again, there have been a huge amount of new projects registrated during the month.

Read more...


Open Source has taken over smart phones

Since the Symbian operating system became open source is now a clear majority of the world's smart phones based on open source...

Read more...

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Newsletter February 2010


Synthesize ORPSoC

We're happy to announce that the ORPSoCv2 project now include scripts enabling it to be synthesized for FPGA. Although this first release contains support for a single Xilinx development board, we encourage contributions of builds which support other vendor FPGAs and boards as well!

This first board build is for the Xilinx ML501 evaluation board, containing a Virtex 5 part. The build contains a 266MHz DDR2 SDRAM controller, ZBT SRAM controller and the ethernet MAC has been set up with the board's phy. This provides a platform to evaluate the OpenRISC with a large high-speed DDR2 memory and network support.

The board build contains scripts providing easy simulation, and a simple one-command synthesis and place-and-route flow. It has been configured allowing easy configuration of the modules included in ORPSoCv2 and easy addition of custom RTL modules and software, specific to each board.

Support for other boards and FPGA vendors will be added in the near future. We encourage other users to develop and contribute their board builds for ORPSoC.

With further upgrades to the OR1200 processor and its peripherals expected in the near future, we hope that synthesizable builds for ORPSoC will allow quick and easy evaluation of any increases in performance and decreases in area and power.

For further information see the readme files (link) in the ORPSoCv2 repository here at OpenCores.org





Apply for "OpenCores Certified Project"-logo

The number of projects being started here at OpenCores is constantly increasing, and we greatly appreciate this. We would like to encourage all project maintainers to ensure that their project is developed to stage where it is considered completed. By this we mean the project contains:

  • RTL design files (VHDL / Verilog / C / assembler / etc)
  • Testbenches (self-checking)
  • Documentation (design and testbench specifications, FPGA/ASIC size information)
  • Make-scripts (compile-, testbench-, synthesis scripts)
  • Information about Design-usage meaning, has it been verified on actual hardware, is it being used in commercial products. This information builds allot of creditability.

To help users identify those projects which have reached this stage, we will now apply a "OpenCores Certified Project"-logo to the project. We hope that this also provide some incentive to developers to fully complete their project, as it likely those projects which have been certified will see greater use.

Those labeled "OpenCores Certified Project" will also be presented on a separate projects list, highlighting these "mature/solid" projects to the maximum.

The procedure to get a project "OpenCores Certified Project"-approved is simple, just send us an email (oc-team@opencores.org) when your project fulfils the above criteria. We will then review your project and apply the certified stamp if it applies.

We have also started to actively clean-up the project list, if a project doesn't have design files checked into the SVN repository after 3 month, then we will contact the maintainer and check the status of the project.





How good are high-level synthesis tools for FPGAs?

In theory it looks very tempting. An expert in DSPs just needs to take their C code and a high-level synthesis tool to access the world of FPGAs where parallelism (almost) gives unlimited performance for a small fee. In reality, it is not so easy, but now experts at the American consulting firm BDTI have benchmarked the tools. And it turns out that at least some of the promises are true.

Berkeley Design Technology Inc., BDTI, with Jeff Bier at the helm, is known to measure the real performance of signal processors. In addition to selling reports BDTI also help clients decide on the right processor.

For several years BDTI has published a report called "FPGAs for DSP", in which they measure the (DSP) performance you can get out of an FPGA. The fact that FPGAs can be 100 times more efficient than a DSP is no surprise. Nor that they are 30 times better in terms of price/performance. But to get there has required hand coding at the RTL level.

For the first time BDTI has tested two tools for high-level synthesis, AutoPilot from AutoESL and Pico from Synfora. More tools will follow.

BDTI has based their figures on two examples and compared the results with those you get from hand-coded FPGAs. They have also compared the results with thos that you get from standard DSP tools.

The first example is a video stream with 720p (1280 x 720 progressive scan) at 60 frames per second. The second example is a receiver for DQPSK, in principle, a complete receiver for wireless communication at a bit rate of 5 Mbps.

Pico and AutoPilot delivered good results, according to BDTI. Both tools were used together with Xilinx RTL tools and achieved the good results without too much work. Both of the tools gave an implementation of the DQPSK receiver which basically required as much resources as a hand-coded solution. Both high-level implementations gave 30 times better price/performance than the corresponding DSP solution for the video example.

Although the high-level synthesis tools were as fast as when you design with conventional DSP tools, BDTI points out that with high-level FPGA tools you still need good knowledge on how to design at the RTL level. Including the synthesis, placement and timing analysis needed to take the RTL code into a working FPGA.

More results are available here (link)

Published by Elektroniktidningen at www.etn.se/50619





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Redesigned OpenCores menu system.
  • Optimizing database accesses.


Server information:

  • Spinning like a cat :-)


Our message to the community:

  • Please make sure that all design-files including documentation are stored the project SVN repository. The "Downloads" page is only meant for pictures or document that are intended to be visible on the "Overview"-page. No design-files are allowed on the "Downloads" page.





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

Hamming-Decoder and -Encoder for 32-bit wide data words
This project consists of two modules which work together: the hamming-encoder and the hamming-decoder. Both modules are combinatorical networks.
Hamming-Encoder:
Input a 32-bit wide data word to the encoder, and the encoder puts 6 paritiy bits to the data bits and 2 additional overall parity bits. The outcoming data word is coded and has a width of 40 bits. It is resistent to a single bit error (will be corrected by the decoder) and even if 2 bits are damaged, the decoder is able to recognize this.
Hamming Decoder:
Feed a 40 bit wide coded word to this decoder, it will read the parity bits and will compare it to calculated parity bits. If there is no error or a single bit error (means that one bit of the incoming 40-bits has not its original value), the decoder will correct the failure and will output a corrected data word. If there are two bit errors, the error-flag goes high to indicate that a not correctable failure is detected. If there are more than 3 bit errors, the decoder is not longer able to check if a bit failure is present on the incoming data, the reason for this is, that the encoder generates a hamming distance of 3 to the data.
Development status: Alpha
License: LGPL
Updates:
Feb 2, 2010: Module description

UART to Bus
The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. The parser supports two modes of operation: text mode commands and binary mode commands. Text mode commands are designed to be used with a hyper terminal software and enable easy access to the internal bus. Binary mode commands are more efficient and also support buffered read & write operations with or without automatic address increment.
Development status: Stable
License: LGPL
Updates:
Feb 15, 2010: Files uploaded to SVN server.
Feb 12, 2010: Updated description of project. Coming soon.

UDP/IP Core
VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication!
Development status: Stable
License: GPL
Updates:
Feb 2, 2010: update description

FFT-based FIR Filter
FFT-based FIR Filter is a unit to perform the finite impulse responce filter based on the Fast Fourier Transform (FFT). It performs the convolution of the unlimited signal sequence with the synthesized impulse responce of the length of Ni=N/2 samples, where N = 64, 128, 256, 512, 1024. The data and coefficient widths are tunable in the range 8 to 18.
Development status: Stable
License: LGPL
Updates:
Feb 2, 2010: added description

Low-Pass IIR Filter
Low-Pass IIR Filter IP core is a unit to perform the Infinite Impulse Responce (IIR) low pass filter which pass frequency is tuned dynamically.
Development status: Stable
License: LGPL
Updates:
Feb 2, 2010: added description

Open FreeList
The Open FreeList module is used to manage a set of variable sized packets inside a fixed memory block. The memory block is partitioned into fixed sized chunks and each packet uses one or more chunks.
Development status: Beta
License: LGPL Updates:
Feb 16, 2010: Bug fix submitted
Feb 3, 2010: Committed code to SVN
Feb 2, 2010: Description changes
Feb 1, 2010: Added project overview

wb_to_amba
A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported
Development status: Alpha
License: LGPL
Updates:
Feb 4, 2010: initial checkin

Pipelined DCT/IDCT
DCT soft core is the unit to perform the Discrete Cosine Transform (DCT). It performs twodimensional 8 by 8 point DCT for the period of 64 clock cycles in pipelined mode.
Development status: Stable
License: LGPL
Updates:
Feb 2, 2010: added description

Pipelined FFT/IFFT 128 points processor
Pipelined FFT/IFFT 128 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 128 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.
Development status: Stable
License: LGPL
Updates:
Feb 2, 2010: added description

Pipelined FFT/IFFT 256 points processor
Pipelined FFT/IFFT 256 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 256 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.
Development status: Stable
License: LGPL
Updates:
Feb 2, 2010: added description





Open Source has taken over smart phones

Since the Symbian operating system became open source it can be said that now a majority of the world's smart phones are based on open source.

Nokia have completed the conversion of Symbian to open source - four months ahead of schedule. Now open source can boast to be the basis for the majority of the world's mobile phones.

During the second quarter of 2009 51 percent of all newly purchased smart phones were Symbian Mobile platforms, according to Gartner. Open source based smart phones will account for even more of the market as Android-based phones continue to increase their share.

For many years people waited for the Linux breakthrough in personal computers, and the operating system has gradually started to make inroads in the so-called netbooks or mini-PCs.

Meanwhile, Linux and other open source platforms have sneaked in the back door to see uptake in a large percentage of embedded systems. In the section of the embedded systems market called smart phones, open source now has market dominance, helped along by the recent conversion of Symbian.

That Android is based on Linux has probably not escaped anyone. Less attention is also that Apple's mobile iPhone is based on open source software - Darwin - which is also used in OS X. Also Palm's Web OS is based on Linux.

The same applies to Nokia's new smart mobile platform, Maemo. It is used in N900 and is the “most open" platform up to date, if we only look at the big companies. Maemo can best be described as a Linux PC in the size of a cell phone. This is in contrast to Android and iPhone OS, which are mixtures of open and owned code, where such information as Iphone identity, user interface, is owned code.

Besides the big names there has been another bunch of Linux Mobile on the market for several years, particularly in Asia. They are based on the standard Limo or special developed versions by companies as MontaVista and FSM Labs.

Samsung's new smart mobile operating system Bada might upset the balance between open and owned code. Bada is a platform that could in principle run under Linux, but the underlying operating system is said to be the Nudeus from Mentor Graphics.

In 2012, 74 percent of all smart phones will be based on open source. That figure is reached if you summarize Gartner's predictions for Android, iPhone OS, Symbian, Web and OS "Linux devices".

In some local markets smart phones based on open source is still in the minority. In U.S. for example Symbian is hardly visible at all. Instead the operating systems owned Blackberry OS and Windows Mobile are dominating. During the third quarter of last year were 22 million U.S. smart phones based on those systems, against 13.9 million in total for Iphone, Webo, Symbian and Android.

Published by Elektroniktidningen at www.etn.se/50642





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