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NEWSLETTER JANUARY 2010

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+70 000 registered users!

We are now close to 73 000 users. The number of users registering an account at OpenCores is increasing...

Read more...


MyHDL - From Python to Silicon

MyHDL is an open source Python package developed by Jan Decaluwe that lets you go from Python to silicon...

Read more...


Publishers – be afraid, very afraid

Mike at Napier blog about OpenCores Media kit: "But the rates for the site are crazy! Prices drop to €0.46 per thousand... About one hundredth of the rates you might get from a typical magazine site!"

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
This month we present +15 new projects!

Read more...


A porting friendly free RTOS

Kelvin Lawson has released his own real-time operating system, Atomthreads, as open source. It is optimized for portability and is ideally suited as an object...

Read more...


Fabless semiconductor companies are taking market shares

Semiconductor companies without own production, so-called fabless semiconductor company, is growing significantly faster than the company's with own factories, and have today...

Read more...

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(c) Copyright Opencores.org, equivalent to ORSoC AB. All rights reserved. OpenCores®, registered trademark.

Newsletter January 2010



+ 70 000 registered users at OpenCores

Since the last newsletter we have passed 70 000 registered users and are now close to 73 000 users. The number of users registering at OpenCores has been increasing, with the rate at almost 3000 per month. During Q3-2010 we expect to surpass the 100 000 registered users mark.

This is great news, as we feel the more users there are, the more the community comes together to share and enjoy everyone's contributions.



MyHDL - From Python to Silicon!

MyHDL is an open source Python package developed by Jan Decaluwe that lets you go from Python to silicon. With MyHDL, you can use Python as a hardware description and verification language. Furthermore, you can convert implementation-oriented MyHDL code to Verilog and VHDL automatically, and take it to a silicon implementation from there.

The key idea behind MyHDL is the use of Python "generators" to model hardware concurrency. Generators can be described as resumable functions.

It's not a behavioral-synthesis tool, but it is more intelligent than just a translator. For example MyHDL supports enumerated types. By adding different attributes to enumerated types, a MyHDL user can automatically change the encoding of a state machine in the translated Verilog.

The converter also supports signed arithmetic, which can be a "nightmare" in Verilog for unexperienced engineers. These issues do not exist in MyHDL. The translator takes care of these things automatically, and can add a signed bit when it's necessary. Verilog users should start taking a look at this, because some of the tasks they face are much harder to do in Verilog directly than they would be in MyHDL.

The MyHDL simulation capability, meanwhile, supports the concept of "unit testing," which is widely used in software development. It basically means that tests are written immediately for any hardware module that's developed, however small. An element such as a finite state machine would thus be thoroughly verified before being integrated into the larger system.

Below are some statements that might be a good reason to use MyHDL:

  • You are new to digital hardware design: Python is one of the easiest programming languages to learn, and MyHDL handles all of the low-level details of VHDL/Verilog.
  • Flexible Designs: MyHDL you can convert your designs automatically to both Verilog and VHDL. So you keep all your options open.
  • You use scripting languages intensively in the design flow: Designing FPGA/ASIC today requires “scripting” languages in your workflow, and Python is a good language to use.
  • You would like to do algorithm development and implementation in the same environment: Python is an ideal language for algorithm development and many engineers use it for this purpose.
  • You think SystemVerilog is too complicated.
  • You are confused about blocking and non-blocking assignments in Verilog.
  • You think VHDL requires too many conversion functions.
  • You're confused about signed arithmetic in Verilog.

More information about MyHDL is available here (www.myhdl.org)





Publishers – be afraid, very afraid

This is a blog written by Mike at Napier, December 9th, 2009

I’ve written in the past about the fact that our industry charges much higher CPMs than you’d see elsewhere. I feel comfortable that this is justified by high-quality editorial written by experts that attracts a very specific niche audience. Despite this, the publications that do invest in great editors aren’t making a fortune. In fact we risk losing a lot of great content from our industry because the current business models can’t support all the great editors that work in electronics.

Current CPMs vary considerably. Let’s say that they run from €20 to €100. At this level advertisers can struggle to justify the investment, whilst publishers can only just pay the bills. Things are just about in balance, with publishers only able to cut prices if there is a huge increase in page views.

Then Opencores.org send me their media pack. OK, I completely accept that the Open Cores website has a very specific audience. Visitors to the site include include a higher proportion of students than magazine sites as well as engineers who are attractive to a relatively small group of advertisers (including the notoriously stingy EDA sector). But the rates for the site are crazy! Prices drop to €0.46 per thousand (you have to buy a sponsorship for a month, and the CPM is calculated based on the average impressions per month). About one hundredth of the rates you might get from a typical magazine site!

In reality I don’t expect Open Cores to change the pricing of “mainstream” sites. But if other user-generated content sites enter the market with very low rates, then publishers are going to find their CPMs under extreme pressure.

Read Mikes blog here





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Fixed "Project maintainer" related bugs (project-properties, project-comments, project-file-upload)
  • Incorrect cache-handling (some field was showing "old-data")

Server information:

  • Performance issues due to the "Incorrect cache-handling" bug. The server performance is now normal again.

Our message to the community:

  • We have now passed the 70.000 registered users and we are of course very happy to see that our services help engineers with their work




New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

Floating-Point Logarithm Unit
VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog algorithm.
Development status: Stable
License: GPL
Updates:
Jan 7, 2010: added the stable version
Jan 7, 2010: edited additional info

IGOR - A microprogrammed LISP machine
- A PCB with all the components of the system: FPGA, AVR microcontroller, IO-units, Memory... the works.
- An implemented processor running on the FPGA.
- Several IO units, connected to the main processor through an AVR mircrocontroller through a parallel bus.

Development status: Beta
License: BSD
Updates:
Jan 2, 2010: Updated the project pages. Added information about the state of the project, what it consists of and who contributed to it.

IPv4 Ethernet Packet Creator and Transmitter
VHDL implementation of a component that can be connected to the input port of the Virtex-5 Ethernet MAC Local Link Wrapper and that allows for transmission of IPv4 ethernet packets.
Development status: Stable
License: GPL

Pipelined FFT/IFFT 64 points processor
Pipelined FFT/IFFT 64 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 64 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.
Development status: Stable
License: LGPL
Updates:
Jan 7, 2010: changed project description
Jan 6, 2010: project details
Jan 6, 2010: added description
Jan 6, 2010: added design files

Direct Mapped Cache Controller Wizardry
This project is to develop a direct mapped cache controller for embedded applications.
Development status: Mature
License: LGPL
Updates:
Jan 6, 2010: Memory Cotroller Design Completed

Software Aided Wishbone Extension for Xilinx (R) PicoBlaze (TM)
This project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or slave cores as an 8-bit master device. Unfortunately there is no native hardware handshake mechanism at PicoBlaze (TM) ports, so wishbone wait-state recognition has to be done by software polling
Development status: Stable
License: BSD

CPU Lecture
This is a lecture about designing a SoC in VHDL. Everything runs under Linux - no more Windows! Check it out and then start at the file named index.html.
Development status: Alpha
License: LGPL
Updates:
Jan 5, 2010: "Additional info" provided

SPI Slave
spislave is a minimalist spislave IP core that provides the basic framework for the implementation of custom spio devices. The core provides a means to write up to 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. A full Icarus Verilog test bench is available
Development status: Stable
License: LGPL
Updates:
Dec 30, 2009: updated description
Dec 30, 2009: edite descriptionq
Dec 28, 2009: changed the status
Dec 22, 2009: added features
Dec 22, 2009: added features
Dec 21, 2009: changed the status from planning to alpha version
Dec 21, 2009: changed the status from planning to alpha version
Dec 21, 2009: changed the status from planning to alpha version
Dec 19, 2009: tested in gtk waveform
Dec 18, 2009: editd the text
Dec 17, 2009: added status for i2clcd
Dec 17, 2009: added description for spi slave

I2C lcd
i2clcd is a minimalist i2clcd IP core that provides the basic framework for the implementation of custom i2clcd devices. The core provides a means to write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. A full Icarus Verilog test bench is available.
Development status: Planning
License: LGPL
Updates:
Dec 19, 2009: status updated
Dec 18, 2009: edited the features
Dec 17, 2009: features has been added
Dec 17, 2009: added description for i2cslave

SPI Controller for AD/DA chips on S3E/A/AN Starter Kits
Modified SPI Master Core by Simon Srot. This core is designed for use with the Spatan 3E, 3A, and 3AN starter kits, for interfacing with the onboard Linear Technology Analog to Digital and Digital to Analog convertors. .
Development status: Alpha
License: LGPL
Updates:
Dec 13, 2009: Uploading initial commit of files

FROM and TO files
For make stimulus of testbench some times need work with files from VHDL. I think that will be very good if some different stimulus will be in one place.
Development status: Alpha
License: LGPL
Updates:
Dec 18, 2009: latest schematic and PCB files are uploaded

DS1621 model
DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and include the macro tasks based on that write/read tasks. A test with macros is included. Only the Slope and the Counter registers are not supported.
Development status: Beta
License: LGPL
Updates:
Dec 19, 2009: Won struggle against SVN. Now the files are in the repository.
Dec 18, 2009: Add files

Huffman Decoder
Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the code have to adapt.
Development status: Alpha
License: Others
Updates:
Dec 18, 2009: first information about the project posted





A porting friendly free RTOS

Kelvin Lawson has released his own real-time operating system, Atomthreads, as open source. It is optimized for portability and is ideally suited as an object of study for those wishing to learn more about operating systems, according to Kelvin Lawson.

The basis of the operating system is a so-called "thread-scheduler” that is, a mechanism that allows you to split your program in parallel executing threads.

In addition, there are mechanisms to synchronize these wires' activities with each other, like semaphores, mutex, queues, and timers. They are for example used to prevent the program threads using the same resources simultaneously.

Kelvin Lawson is an embedded developer based in London.

- Originally, I used Atomthreads as thread scheduler for some projects within home automation. But then it grew into its own project, says Kelvin Lawson through Facebook.

If you currently have a single-threaded program that would grow into multi-threaded, just download Kelvin Lawson's source code library and kick off the threads.

The licenses for Atomthreads is BSD-like, meaning you can make modifications that you - unlike those of Linux - do not have to share.

Today is the AVR ATmega processor supported. Kelvin Lawson says on his blog that it is fairly easy to add support for additional architectures, as he minimized the use of AVR-specific functions, just to make porting easier.

Which also means, he admit, that there are other operating systems that are more effective than his, if you are looking for an operating system for the AVR?

To further facilitate porting to other processors, he has developed an automated test suit that verifies the basic functionality of the operating system is functioning properly.

His source has been rated "well documented" and he suggests that it can be used as teaching material for those who want to learn the basics of operating systems.

Published by Elektroniktidningen at etn.se/50528





Fabless semiconductor companies are taking market shares

Fabless semiconductor firms have increased their market share over their counterparts, according to updated market share figures from IC Insights. Semiconductor companies without their own silicon production capability, so-called fabless semiconductor companies, have been growing faster than their IC manufacturing counterparts, or integrated device manufacturers (IDM). Figures show they now account for 23 percent of the global semiconductor market. Nine fabless semiconductor companies managed a turnover of more than one billion U.S. dollars in 2009, according to a report from IC Insights.

Qualcomm remained at the top of the list of the world's largest fabless IC companies, released by IC Insights showing figures from 2009. Second on the list was fabless newcomer, AMD, now classed as receiving a majority of its finished wafer supply from IC foundaries after divesting of its fabs to Abu Dhabi-controlled Globalfoundries Inc.

However, the fastest growing company last year was Taiwanese consumer IC designer MediaTek, which increased its sales by nearly one billion U.S. dollars last year to 3.5 billion U.S. dollars.

Overall, U.S based companies dominate this niche, with those in Taiwan a close second. Of the 25 largest companies, 17 were from the U.S, 6 from Taiwan and only one each from Europe and Japan. The European contribution is the bluetooth specialist CSR who, having reduced losses to 14% in 2009 from 18% in 2008, have slipped down three positions compared to last year to 15th place.

The 10 years from 1999 to 2009 saw fabless semiconductor companies grow faster and more steadily than their IDM counterparts. The average growth per year has remained at 15 percent, compared with 2 percent for factory owners. The fabless niche now accounts for 23 percent of semiconductor sales worldwide and, according to IC Insights, further expansion should see its share rise to 27 percent in the next 4 years. Several major semiconductor manufacturers such as LSI, Agere and IDT, have plans to follow in AMD's footsteps, opting for wafer fabrication from from third-party foundries

The overall declining trend in IC sales revenue for 2009 didn't impact on the fabless sector as much. The ten largest (AMD excepted) declined by only 4 percent, compared to the decline of the semiconductor market as a whole by 11 percent.

Top 25 fabless 2009

Published by Elektroniktidningen at etn.se/50512





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