Newsletter November 2009
In the OpenCores community the Linux environment is very popular. Amongst the most commonly used distributions is Ubuntu. In the latest release of Ubuntu, 9.10 Karmic Koala, the official repositories no longer contain the Verilog Preprocessor VBPP. To ease installation of this highly usable preprocessor OpenCores will distribute Ubuntu packages. There are two versions available, 32 and 64 bit..VBPP is a Verilog preprocessor. It has support for most Verilog preprocessing directives and additional directives such as:
- Statement generator ('generate' command in VHDL)
- Expression evaluation
- Mathematical functions: log2, ceil, floor, round, abs, etc.
- Conditionals: if, switch, etc
To install in Debian based distributions such as Ubuntu:
sudo dpkg -i vbpp_1.1.0-6_amd64.deb
This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
This month activities:
Fixed SVN revision mismatch between SVN and WebSVN.
Power-supply failure. Switched to the backup server for 1-day during the repair installation.
Our message to the community:Please let us know about empty projects, older then 1 month calculated from the "created date".
Here you will see interesting new projects that have reached the first stage of development.
Quadrature Decoder (for optical Encoders)
VHDL Implementation of a quadrature decoder module with a Wishbone bus interface. This module has the following features:
--Wishbone module for interfacing to optical encoders
--4X Quadrature decoding of encoder signals
--Programmable external interrupt request output
--Dedicated 'latch quadrature count' input for multi-axis syncronization
--Memory mapped control, status, and count registers
--Verified on a Xilinx FPGA with a soft core processor (Altium TSK3000)
Development status: Alpha
Nov 7, 2009 uploaded file
Nov 7, 2009 Update description on main project page; planning initial check in.
i8255 realisation in Verilog
Complete implementation of i8255 PPI in fpga.
Development status: Alpha
Nov 22, 2009 Updated svn with assignments fixes. Code contains a lot of junk entities and useless stuff - it's all for the future or just my old thoughts.
Nov 22, 2009 Updated description.
Nov 22, 2009 I'll upload entire Xilinx project soon.
Nov 21, 2009 Uploaded svn. There are only two files now: device and testbench. Supports only 0 mode for Group A and Group B. All signals same as in real device(inverted too). Warning: 'data' must be provided before nWR will be placed on the pin in write mode.
Nov 21, 2009 Updated Description with link to datasheets site.
Nov 17, 2009 And excuse me for word 'realisation' with s instead of z))))
Nov 17, 2009 All operations are triggered by the nRD or nWR, when nCS comes to the pin.
Nov 17, 2009 I 'll upload ones around week. Status: realisation of Group A port A completed.
16-bit CPU based loosely on Caxton Foster's Blue architecture
A 16-bit classical CPU based loosely on Caxton Foster's Blue CPU from the book "Computer Architecture". Includes a cross assembler and a very novel front panel for the Digilent Spartan 3 board.
Development status: Stable
Nov 23, 2009 SVN seems to have quieted down
Nov 22, 2009 Files were checked in but SVN sporadically "loses" them -- email sent to admin
Nov 22, 2009 The BLUE8 Project was approved. I'm prepping the first release of files to upload.
Theia: ray graphic processing unit
Theia, is a programmable graphic processing unit (GPU).
It has a ray-cast approach to rendering, using internal fixed point arithmetic to accelerate the graphic pipeline. Programming capabilities include several stages of the graphic pipe, such as texturing, space partitions, intersection tests and others.
* Programmable shaders using custom assembly instructions: It has arithmetic instructions to operate on R3 vectors, data movement instructions and branch control instructions.
* Pipelined SIMD ALU: custom ALU to operate on 3D instructions.
* Wishbone compatible IO.
* Build-in (default) ROM code for:
1 - Spatial subdivision algorithm: AABB partition.
2 - Texturing: simple Bilinear filter.
3 - Lights: simple Phong.
Development status: Stable
Nov 25, 2009 Adding initial files to SVN
Nov 23, 2009 Added initial project description.
The Wizardry Project
Wizardry, an open source network intrusion detection system, provides protocol analysis as well as deep packet inspection. Target for the Virtex 4 FPGA platform, this project includes several hardware components that enable basic network intrusion detection functionality:
The Embedded Protocol Analyzing Classifier (EmPAC) is designed to perform the task of packet classification through protocol analysis. Its goal is to take an unclassified byte stream coming from the Ethernet Physical Layer Interface (PHY) and partition and classify the data blocks into corresponding protocol fields. These include header information such as source and destination address, header and payload sizes, and protocol flags, as well as the payload fields themselves.
The Enhanced Reconfigurable Content Process (eRCP) is a processor designed as a component of Wizardry to perform the task of inspecting incoming preparsed Ethernet frames for matches to Regular Expressions.
The Reconfigurable Double Data Rate Synchronous Dynamic Random Access Interface Memory Controller (RDIC) provides each component of Wizardry with priority-based Wishbone compliant access to shared memory resources. Each device may access the shared memory space of other components, along with its own personal private (read and write) and reserved (read only) portions of memory. RDIC supports up to 8 separate Wishbone compliant devices.
The Java Optimized Processor (JOP) is an open source Java Virtual Machine implemented in VHDL that provides an interface to the FPGA. JOP also enables configuration of other components included in Wizardry. This component has write access to the reserved memory space of each component (for configuration data), and has read access to the shared memory space of other components (to retrieve results and output from each component).
The Web Server provides an interface into the NIDS for the user. As the front end of the Wizardry, the Web Server contains web pages that allow the user of Wizardry to configure modules and view statistics about the state of the FPGA.
Development status: Mature
Nov 17, 2009 Corrected project properties
Nov 17, 2009 Updated project description
JPEG Encoder Verilog
This core takes red, green, and blue pixel values and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores, instead all of the functions required to implement the JPEG encoder are written in Verilog and the code is entirely self-contained. This core has been simulated on many raw images with different quantization and Huffman tables.
Development status: Alpha
Nov 16, 2009 Posting source code
Next year, the semiconductor market will grow by 13 percent and then reach the same level as 2008, around 255 billion dollars, according to the industry analysis house Gartner.
Increased demand for PCs has driven the semiconductor sales this year and the market is not as bad as Gartner believed previously. Gartner, therefore, raises its forecast for the year from minus 17 to minus 11.4 percent, compared with last year.
In addition to memories and microprocessors for PCs, ASSP (Application Specific Standard Products) have grown stronger than expected. The mobile market has also stabilized, resulting in increased demand for NAND flash.
- The outlook for both DRAM and NAND flash has improved as prices have been reinforced more than in our last forecast, says Bryan Lewis of Gartner in a statement.
For next year, Gartner expects to track continued growth of about 13 percent. This would then mean that the world market by 2010 would have staged a full recovery to 2008 levels, or around 255 billion dollars.