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NEWSLETTER OCTOBER 2009

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Broker Services

OpenCores is offering a service to help companies find the right resources for their needs, and help all engineers connected to the community find interesting jobs/projects all over the world

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Job Opportunity

Available assignments:
- (NEW) Algorithms for H.264 video encoding
- Digital HW Designer, Wireless RBS
- System architect, Wireless RBS
- System Engineer, Wireless RBS
- Engineer, monitoring and control
- Cabinet, rack Design Expert
- RF Mechanical Design Specialist
- Senior Power Distr. Engineer
- Power Supply Engineer (Board)
- Power Supply Engineer, Efuse
- Manager, Radio Access Network

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Extended statistics

OpenCores have extended the stats related to each project. It is now possible to see the experience profile of all users who have downloaded a project.

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Free Magazine Subscriptions & Technical Document Downloads

OpenCores has partnered up with Tradepub, to provide all OpenCores users with free technical magazines and other documents of interest.

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Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

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Updated and new IP-cores

View a list of some of the projects that has been updated during the last month. Here you will also see interesting new projects that have reached a first stage of development.
This month we present 4 new projects & 3 updated

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Newsletter October 2009



Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:
Added more statistic for each project.

Server information:
No failures or problems.

Our message to the community:

  • Keep up the good work




Updated and new IP-cores

View a list of some of the projects that have been updated during the last month. Here you will also see interesting new projects that have reached the first stage of development.

NEW PROJECTS:

Modbus RTU (serial)
MODBUS is an application layer messaging protocol for client/server communication between devices connected on different types of buses or networks. MODBUS is a request/reply protocol and offers services specified by function codes. It has become a de facto standard communications protocol in industry, and is now the most commonly available means of connecting industrial electronic devices. Development status: Planning
Updates:
Oct 19, 2009: Description update

wb_uart
Implements a 16550/16750 UART. The UART core is taken by another OpenCores project. The interface is now compatible with a 8-bit WishBone bus.
Development status: Alpha
Updates:
Oct 12, 2009: Uploaded files

RTEA 128/256
RTEA (from Ruptor's TEA or Repaired TEA) - a symmetric block encryption algorithm used type "Feistel cipher", designed by Marcos el Ruptor, expansion TEA. Fixed some vulnerability in the algorithm. Like other variants of the algorithm TEA, the operation based on work with 32-bit numbers
Development status: Stable
Updates:
Oct 5, 2009: SVN upload
Oct 5, 2009: Description update

LogOS
The LogOS is an OpenSource Logger core, written in Verilog. This useful engine for comfortable grab and watch HiSpeed Digital (in future - also Analog) Signals. It is based on following technology:
- Unified transport layer: Ethernet, CAN, etc..
- Unified metacommand set
- VCD-format for convenient work with data
Development status: Planning
Updates:
Oct 20, 2009: add short Description


UPDATED PROJECTS:

Cache: Cache Architecture for Configurable Hardware Engine
No description
Development status: Alpha
Updates:
Oct 18, 2009: Major updates: 5 dot-product executions are completed without error.
Oct 12, 2009: Minor updates: Fixing error of long vector loading that made invalid acquirement.
Oct 6, 2009: Strict Stack Shift model is completed.

CAN Protocol Controller
Controller Area Network or CAN is a control network protocol from Bosch that has found wide use in Industrial Automation and the Automotive Industry.
Development status: Stable
Update: No information available

TV80
The TV80 is an 8-bit Z80-compatible microprocessor core, written in Verilog. It is based on Daniel Wallner's VHDL T80 core.
Development status: Mature
Update:
No information available





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