An OpenRISC Update

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An OpenRISC Update

With new life being breathed into the OpenRISC project of late, it's time for an update on what has been going on, and what is to come for OpenCores' flagship project.

One of the most important elements of any embedded processor is the ease of development, implementation and debugging. Ever increasing use of the processor in both academic and industrial fields has resulted in better toolchain support, ready-to-go development models and debugging tools. Better yet, current work will see increased performance and support for the OpenRISC port of the Linux kernel. However, more application specific implementations of the OpenRISC are also in the works, with the OpenCores very own H.264 Encoder SoC project forging ahead, making great use of the existing tool set, as well as making valuable contributions.

Toolchain Improvements
The OpenRISC processor toolchain has received upgrades and expanded capabilities. The addition of a port of the latest version of the newlib C library built for embedded use, and better floating point support in the compiler means more options, and complements the existing uClibc port perfectly. The automatic installation script has eased installation woes, making is quicker and simpler to get up and running. See the OpenRISC's toolchain page for more information.

Simulation models and ORPSoC
Work never ceases on ORPSoCv2, or OpenRISC Reference Platform SoC version 2, which is an example SoC based around the OpenRISC processor with Wishbone interconnect, including sample software and sample simulation options. It includes the RTL design, but also makes use of the architectural simulator, or1ksim, and contains an example library of software which tests the system. The ORPSoC project aims to provide a simple entry point for users of the OpenRISC architecture.
ORPSoC can be simulated using an entirely open-source (free!) tool set, as well as supporting proprietary Verilog RTL simulators. However, in addition, a cycle-accurate model can be created easily, delivering the speeds of commercial simulators with none of the cost!
Improvements of note in ORPSoC lately include several functions added to the cycle-accurate model (better VCD and memory contents dumping, ELF file loading, profiling generation similar to or1ksim) and of note is the improvement of the accuracy of execution statistics (exactly the same as event-driven simulation). The SoC now contains an FPU inside the OR1200, an RTL arbiter, and easier-to-use user interface. More are in the works too, so check back soon.

OpenRISC Linux kernel port
Work is underway to bring one of the latest Linux kernels to OpenRISC, with increased stability, performance and usability. The latest version of the BusyBox applications are running on top of the kernel, and we hope to release this soon to update the existing BusyBox port. But what are available now is a complete guide to kernel compilation and use on target (http://opencores.org/openrisc,linux_busybox) , and RAM disk generation for a simple OpenRISC-based system (http://opencores.org/openrisc,linux_ramdisk)

H.264 Encoder Project
Currently in its infancy, the OpenCores H.264 baseline encoder project aims to develop an OpenRISC-based SoC capable of performing basic video encoding. The project has taken the step of evaluating one of the best software H.264 encoding implementation available, x264. This encoder software has been ported to OpenRISC and an approach where this software is accelerated via use of custom hardware modules is currently being evaluated. Ideally this process of accelerating the software will result in modules with a specific encoding job to do, which can operate in parallel, creating a heterogeneous processor system, ripe for today’s modern reconfigurable computing platforms such as FPGAs.
The project currently has many contributors, but of late has seen a slump in activity. We hope to see progress pickup as the approach is finalised and implementation and testing begins!

By: ORSoC