Hi, all.

I need to interface my PicoBlaze with my USB-FTDI cable so I can dump ASCII to my PC. Is there a very simple core (hopefully in VHDL) that I can use to get up and running quickly? I tried the MUART, but I'm getting bogged down in that.

Thanks!
Ross

The Advanced Debug System includes a "JTAG Serial Port". It looks like a 16550 UART on the SoC system bus, but it transfers the data via the JTAG cable. The ADS won't control the picoblaze processor, but you can still connect the JSP (and the WishBone controller, if you want) and send/receive data using adv_jtag_bridge and a telnet program. ADS includes drivers for FT2232 and FT245 cables, if that's what you've got.

Thanks for the response, nyawn. I'll have a look.

Sounds like it's a little heavy for my needs...I simply want to dump ASCII up my FTDI connection. I only need a fixed baud rate too, so I may just build up a little VHDL around a FIFO module I'm using for other stuff, and just hack out the serialization + start and stop bits...easy stuff. Can probably do that quicker than exploring a JTAG system or the MUART's several components.

One question, may be OT: Are the CTS and DTS signals important, or may I tie them 'true', guessing high?

Thanks!
Ross

Oh, one other thing: I've got my PicoBlaze running with a Wishbone bridge (master) and I have it addressing a WB slave that connects to LEDs on my Xilinx FPGA breakout board...all works fine. I now want to make another WB slave with the four FTDI signals on the non-bus side.

Ross

I know this one works: http://opencores.org/project,sasc

Richard

I think what you describe here is exactly what the JSP is...4 wires from the FTDI JTAG cable on one side, WishBone slave (with a 16550-style register interface) on the other.

Regarding your other post: At least in the case of the JSP, the serial handshake lines are completely unused...there is no asynchronous connection, so they're not needed. The only important thing is are there bytes in the FIFO to read, and is there space in the FIFO to write, and this is indicated in different status bits for a 16550-style WishBone slave.

I think if you try to hack it yourself, you'll find it harder than you think...you have to coordinate a pair of FIFOs between two clock domains (one with a slow, irregular bit-bang clock), the FTDI will have to poll for data, you'll have to write software on the PC side to do the polling, etc. Look at the JSP module in the advanced debug system to give you an idea. Or, you could just start by using the JSP module - The BIU portion is pretty well self-contained, with a clean interface, and takes care of the clock domain coordination, the FIFOs, and the 16550-style WishBone slave interface. You would just have to do the serial-to-parallel on the FTDI lines...though by the time you finished, you'd have mostly re-implemented most of the debug system anyway! (You can also use the FTDI driver from the adv_jtag_bridge program, if you end up writing the PC-side client yourself.)

A very simple UART can be found in the c16 opencores project. I used the same simple UART in my project: uart to bus. The UART is very simple and small but does not include any FIFO or registers. The baud rate is set using constants.

Moti

Hi Ross,

I had used a custom made UART, very simple in design (VHDL) in my thesis project last year. It was fully synthesized and had no violations! There is a process in the code which can be modified to select the baud rate as per needs.

If you still need it, you can send me a mail : debayanpaul@yahoo.com

Cheers,
debayan