Hi, is anyone familiar with the miniMIPS project?
I'm looking at the functional simulation of it, and it appears that miniMIPS have some issues with the memory, it seems it will lose some instructions read from memory, and the decode stage takes 2 or 3 clock cycles just working on the same instruction.

an example:

loading a constant into a register with LI, it gets translated to this:
LUI $9...
ORI $9...

These two instructions work on the same register, so there is a read after write hazard, but there is a bypass unit in miniMIPS, it should be able to proceed without stalls, but what I am seeing in simulation is that the decode stage somehow interprets each instruction for 2 clock cycles.

Has anyone verified miniMIPS to be what it says it is? Or be able to run it with Altera FPGA?

THanks.

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