Read through the Q&A below and if you still got a question, send it to:

Question: When will the ASIC be available to the donors?
Answer: The plan is to have the OpenRISC tested and ready to be shipped to the OpenCores donors by 2013/14.

Question: What ASIC process (geometry) are you aiming at?
Answer: The smaller ASIC process geometry the better, from both a performance, power and unit cost perspective. However the NRE-cost (meaning one-time manufacturing cost) becomes more and more expensive moving to smaller ASIC process geometry. This is the reason why we need to see how much money we can raise from the community, so that we then can decide what ASIC process we can afford.

Question: What will happen with the donated money if it do not reach a limit where it is possible to develop/manufacture an ASIC?
Answer: There are many different ASIC technologies available today with different NRE costs releted to it (Gate Array ASICs, Structured ASICs, Standard Cell ASICs). Our goal is to implement the design into an Standard Cell ASIC, since this will provide a lower unit-cost. If the donation money do not reach a level where we can't even to a Gate Array ASIC, then the money will used to upgrade the server hardware and Opencores and to continue to improve and add new features to the OpenCores website.

Question: Why not list the NRE estimate and per unit price for Structured ASIC (eASIC like ?), Standard Cell ASIC ? As a potential donor I would like to first understand how much money you are aiming to raise.
Answer: Est. Gate-array ASIC NRE: $35.000 - $150.000 : Est. SA ASIC NRE: $35.000 - $250.000 : Est. Std-ASIC NRE: $175.000 - $750.000
There are also allot of other parameters that need to taken into account before deciding which technology to use, for example, performance, power, area, IO count, wafer size, minimum wafer order, est. annual volumes, respin risk management, signal integrity and of course a very important item, unit-cost.

Question: Do you have the team that will do the work ? It would be helpful to know the credentials of the team and judge for one self if they can pull it off. Since this is not a committed project you may not choose to list names; the team's expertise and experience would be sufficient.
Answer: Yes we have a team that have designed many OpenRISC based SoC-design for commercial customers, but we would be really happy if the community want to help out with this SoC-ASIC. We are a team of 15 engineers with extensive knowledge/experience within FPGA/ASIC design with focus on IP-cores from OpenCores. The majority of the engineers have +10 year experience of complex SoC design. Within the grop we also have unique expertize within different areas ie. processor/dsp development, multimedia, ethernet etc.

Question: Under (roughly) what conditions will the ASIC be available to the donors?
Answer: We want to provide the ASIC to the donors at the lowest-cost possible (at cost price plus admin/shipping/inventory costs). The major difference that we want to challenge the industry with, is that we want to have a flat-price regardless of volumes. The price-level will set accordingly based on the accumulated annual volume, meaning that all will benefit if the volumes goes up, not only a specific buyer. We want it to be a joint-venture trying to increase the overall volumes which will lead to even lower unit-costs. This also means that smaller companies can compete with larger companies on fair condition, meaning that they will get the same price for the ASIC and that they will then compete of which product is best from a functionality standpoint.

Question: Does it matter how much you donate?
Answer: No, it's more important that many people donate. That said, it is however also very important that we raise as much money as possible, so larger donation amount are very very very important as well.

Question: Will it only be the (hopefully packaged) chips that are available, or will donors get a good deal on some prototype board?
Answer: The plan is to first offer the ASIC as package-ASICs and also mounted on a development board, and then of course also offer it as bare-dies if needed. The development board will also be offered to the donors with a price as low as possible. Our aim is to develop a "true" open-source ASIC device from start to end.

Question: How are you planning on handling the verification? (I could see that it would make sense to setup some sort of daily regression test and hope that the community could come up with some tests to increase the test coverage of the system.)
Answer: We have regression-test suites for several specific functions/cores. We need for sure to add more system level regression-test suites and this is something that it would be great if the community wants to help out with. And since allot of universities has got all the commercial EDA tools it would be really good if we could get an OVM test-system up and running.

Question: Is there any unique detail to this system that makes it extra useful for some kind of applications? Besides the (hopefully) low price point that is?
Answer: Since we do not yet know what kind of ASIC technology, it depends on how much money we can raise. This means that we do not know if we can include a multi-processor design or not, and how many other peripherals that will fit, without reducing performance to much or becoming to large. Our plan is to try and make it fairly generic so that it can match as many applications as possible, and they we plan to have an extension-interface to that it is possible to use an FPGA outside to handle additional functions (HW-accelerators etc).

Question: "This ASIC will then be offered for sale to the community to use freely in any products, especially for the donors...". What does this really mean? What will be the result of this initiative? Verilog SoC description optimized for ASIC, routed design, dies to buy or even orderable packaged SoC? And what will be special for donors?
Answer: Our aim is to develop a "true" open-source ASIC device from start to end. How much that can be released also depends on what ASIC technology that we can afford. The plan is to first offer the ASIC as package-ASICs and also mounted on a development board, and then of course also offer it as bare-dies if needed.

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