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iwb bus problem

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Information:
Type :: BUG
Status :: CLOSED
Assigned to ::

Description:
bug1:
ConditionF
ICACHE disable;
reset to 0x100,
opcode=0x0 @ 0x100, that is J (N=0),
iwb bus iwb_ack_i latency is random caused interconnect.

Expect result:
PC jump taken once only after iwb bus iwb_ack_i=1

Real resultF
PC jump taken more than once after iwb bus iwb_ack_i=1


Bug2F
ConditionF
ICACHE disable;
reset to 0x100,
opcode=0x0 @ 0x100, that is J (N=0),
iwb_ack_i latency is random caused interconnect.

Expect result:
iwb bus always read 0x100.

Real resultF
iwb bus not always read 0x100, but after several read 0x100, begin to read 0x104 and 0x108 and so onc.

Comments:

Admin, OpenCores Nov 2, 2010
Fixed this in the OpenRISC v3.

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